ON Semiconductor Meets AEC Challenges With Electrothermal Analysis

By Justin Yerger, ON Semiconductor, and Ahmed Eisawy, Mentor, a Siemens Business

ON Semiconductor is a leading provider of products for automotive applications that follow the Automotive Electronics Council (AEC Q-100-012) requirements for reliability characterization of smart power devices. In particular, Automotive Smart FET driver ICs present verification challenges when verifying short circuit reliability. These ICs are deployed in many automotive applications, including bulb/LED and solenoid/actuator loads and relay and fuse replacement. In addition to meeting AEC requirements, these FET drivers must work in harsh operating environments, such as operating in the -40 to 150° C temperature range, and they need to have a life expectancy of over 10 years.

Verification challenges
The AEC defines common electrical component qualification requirements for automotive ICs. For the FET driver IC, the applicable requirement is AEC-Q100-012, which covers short circuit reliability characterization of smart power devices. The purpose of this requirement is to determine the reliability of “protected” drivers when operating in a continuous short circuit condition. With respect to this requirement, a short circuit is defined as a constant overload condition in the load circuit that:

• Draws current in excess of the device over-current limit, unless the power device under test reacts according to its embedded protective functions; or
• Results in excessive device current that triggers one or more embedded device protection functions.

In particular, ON Semiconductor needed to verify thermal shutdown and delta thermal shutdown for the device. Independent hot and cold sensors create a delta shutdown. The device establishes a slow junction temperature rise by sensing the difference between the hot and cold sensors. ON/OFF output cycling is designed with hysteresis that results in a controlled saw tooth temperature profile (Figure 1). The die temperature slowly rises (DTSD) until the absolute temperature shutdown (TSD) is reached around 175° C. The device cycles at TSD with hysteresis until the short circuit is released.

Figure 1: Thermal shutdown with controlled saw tooth temperature profile.

The verification challenge is that it is difficult to simulate the actual transient delta temperature without using ideal sources.

The verification solution
In high voltage/power applications, the control of temperature and its propagation throughout the circuit and the system becomes critical. Using a global uniform temperature for the entire IC is no longer accurate enough. Devices consuming power tend to heat and this heat propagates to neighboring devices though thermal coupling. The temperature at which a device operates modifies its electrical characteristics. Characteristics, such as leakage currents, might have exponential dependencies on temperature.

As the electrical characteristics change, so does the dissipated power and heat. The electrical performance and the temperature are linked together and cannot be calculated in isolation – the electrical and thermal equations are tightly coupled. ON Semiconductor deployed Eldo Platform and its unique electrothermal analysis capability to solve this problem (Figure 2).

Figure 2: The Eldo electrothermal analysis flow.

Electrothermal analysis allows the local temperature of devices or entire cells (SPICE sub-circuits and Verilog-A modules) to be true variables of the system and are solved simultaneously with the voltages and the currents through the devices.

Without electrothermal analysis: previously, ON Semiconductor used ideal sources in order to mimic the relative change in temperature of different circuit blocks such as temperature sensors and power devices. Using the VARTEMP option in Eldo Platform enabled dynamic temperature change simulation, but the ideal sources masked potential problems due to temperature-based transitions including stability, hysteresis, and relative offset.

With electrothermal analysis: in the current ON Semiconductor solution, the ideal sources are removed and the circuitry responds intrinsically to changes in power dissipation (temperature). The electrothermal capability (Figure 3) allows “closed loop” analysis, without intervention by designers, of high power events under any worst case condition. This is critical to reducing the number of design optimization iterations.

Figure 3: Using electrothermal analysis.

The ON Semiconductor packaging team created a die-level thermal model using a Foster network to estimate the package-level thermal performance of the die. The design team created a short circuit simulation testbench and the hot/cold sensors were thermally connected. The power dissipation of the power FET controls the top node of the thermal network.

Verification results
Figure 4 shows the simulation results. The thermal cycling is dependent on power dissipation of the power FET and the thermal network model. Temperature is always rising with pulse cycles and this rising temperature causes the device to turn off in cycles (saw tooth pattern) as predicted in Figure 1.

Figure 4: Simulation results.

The simulation results were compared to silicon by duplicating the testbench on silicon and validating the results. This showed that the simulation results align closely with the actual silicon measurements.

ON Semiconductor’s circuit verification flow needed to follow the complex requirements from the AEC-Q100 standard for reliability characterization of smart power devices. They employ the unique electrothermal analysis capability in Eldo Platform to improve simulation of power pulse events, such as repetitive short circuits and repetitive clamping. By using a die-level thermal model and electrothermal analysis, it is possible to transiently control the temperature of different sub-circuit blocks dependent on the power dissipation of the power of any sub-block in the design.

For more information about this project, see the whitepaper here.