Solving CSD Verification Challenges

To tackle power consumption and slow execution, modern computational storage devices (CSD) seek to reduce data movement by including a small processing element next to the CSD (figure 1). The data request from the host is executed locally by the processing element, data is locally manipulated, and the result sent back to the host. Much less data is exchanged between storage and host, thus saving power, increasing performance, and accelerating the execution.

Fig. 1: Computational storage model.

But, computational storage faces serious verification challenges:

• An application processor (Arm A51, for example) might now be required to manipulate the data on the storage device, in addition to the real-time processing required in a traditional SSD.
• The challenges of verifying performance and latency targets for the device are now exacerbated by sharing internal interfaces with the applications processor.

These challenges lead to a troubling situation where teams believe that they have 100% verified that the system is functionally accurate, yet it fails in the lab because the performance of silicon is far from predicted.

Designers need a methodology to ensure that latency, power, and performance can be deterministically analyzed before silicon. The presence of a processing element in CSDs, embedded software, and the addition of an entire Linux stack with running applications makes this verification task challenging.

That is why Mentor, a Siemens business, created a computational storage verification methodology centered on hardware emulation. The primary reason to use emulation for verification is to run at speeds even software engineers can appreciate, with full visibility. Using a virtual environment enables them to measure design performance and latencies within a few percent of actual silicon. The ability to measure the pre-silicon performance of the hardware and software running as they would in the real product is critical to success. Virtual interfaces connected to the DUT in the emulator provide real-world stimulus and give the verification and software teams the confidence that the design is functionally correct and meets the IOPS, bandwidth, and latency targets required for the product to be successful.

Introducing virtual computational storage verification

Figure 2 illustrates a CSD in an entirely virtual emulation environment with modular components representing the overall system. The system is an SSD controller DUT running on the Veloce emulator driven by a virtual NVMe/PCIe co-model host that generates real-world traffic. Wrapped around the DUT are all the interfaces and models necessary to provide host stimulus and store the data in a NAND model. The entire environment provides seamless hardware and software debug environment, with 100% visibility of all signals and software.

Fig. 2: A scalable, modular storage controller verification system.

Unique elements of the CSD verification methodology include:

• Veloce soft models enable pre-silicon verification of SoCs with multiple interfaces connected to peripherals and host devices.
• Codelink is a software-driven hardware verification solution tightly integrated with Veloce. Codelink’s advanced tracing technology automatically captures and compresses all the critical activity inside a design’s processors during emulation. Verification engineers can “playback” the simulation or emulation run with features such as fast forward, rewind, replay, pause, zoom-in, single step, and pan.
• Veloce NVME Protocol Analyzer is a powerful application to monitor throughput. It decodes each layer of PCIe and NVMe traffic. By processing NVMe Read and Write operations, designers can use the application to calculate and plot throughput. They can measure NVMe command response and display them in a detailed table view and review statistics like maximum and minimum performance and response.

Emulation-based virtual verification provides complete system verification, including full firmware validation. Emulation reduces find-fix-test debug cycles to hours instead of weeks, accelerating time-to-market. From host traffic generation, virtual debugging, Protocol Analyzer on the interfaces, and the ability to view any waveform signal, this new methodology provides the ability to do complete system verification much earlier in the development cycle. This methodology allows for pre-silicon performance and latency testing within 5% of actual silicon, based on customer feedback. It is a verification methodology that mirrors the tools that teams use in the lab for bring-up and system tests.

To learn more, download our whitepaper, “Virtual Verification of Computational Storage Devices.”