SPIE – Day 4

Day Four at SPIE Advanced Lithography began with the much-anticipated presentation by ASML on the NXE:3100 extreme ultraviolet (EUV) “pre-production” lithography scanner. As expected, it was by parts marketing pitch, pep talk, and soothing reassurance that everything is under control.


This week in San Jose began cold, but warmed up by Thursday to the kind of weather we all expect from California. So too with the conference, and I think Thursday had some of the most interesting, and surprising, presentations.

The day began for me with the much-anticipated presentation by ASML on the NXE:3100 extreme ultraviolet (EUV) “pre-production” lithography scanner. As expected, it was by parts marketing pitch, pep talk, and soothing reassurance that everything is under control. The first of six NXE:3100s shipped to Samsung last year, printing its first wafers in December. The second 3100 is being installed now at Imec in Belgium. The other systems will roll out in about two month intervals. Unfortunately, there was no official word (or data) from the system as running at Samsung, but ASML provided a good overview of the performance of the systems at the ASML factory.

You have to give ASML a lot of credit – they know how to build a good tool. The lens quality, resolution, defectivity, and overlay performance was as good as anyone could expect as this point. The “tool flare” was down to 5%, but be careful – the total flare seen at the wafer is the tool flare plus flare caused by the mask and REMA masking blades. This total flare is chip-layout dependent, and was as high as 12% for a Flash chip example they showed (you had to be very close to the screen to see the small “12” in the legend of the graph, but at least it was there).

The performance of the tool was very good, except for two problems. The linewidth roughness (LWR) of all their images was very bad, though not a single LWR measurement was shown in the presentation. But it was the throughput that everyone was most interested in hearing about, and that number was 5 wafers per hour. Of course, that is not a “production” throughput number, since it assumed a 10 mJ/cm2 resist and didn’t expose any edge fields, but it’s still a benchmark number to compare to. It’s better than I thought it would be, but still a factor of 12 from the tool spec of 60 wafers per hour. ASML sought to reassure the skeptical members of the audience by renaming their roadmap for source power an “upgrade path” instead.

As anyone who has known me for a while already knows, I am a skeptic of the viability of EUV lithography for IC manufacturing. It’s not that EUV can’t work, it’s just that the effort required to make it work doesn’t line up with the timing and cost needs of chip manufacturers. When serious work first started on EUV lithography in the mid 1990s, the target insertion into manufacturing was the 130-nm node. Since then, the target has slipped by at least two years for every three years of effort. Today, Intel talks about inserting EUV into manufacturing at their 10-nm node four years from now. The result: tool development has been shooting at a moving target, which is almost always a recipe for disaster.

The 10-nm node for logic means a 20-nm or 22-nm half-pitch, which puts the k1 factor for the half-pitch below 0.5 on the (newly increased) 0.33 NA production tool. This means off-axis illumination will likely be required, and it will be difficult to extend the tool to the next node. Mask blank and patterned mask defectivity is still an unsolved problem, and thanks to a lack of appropriate mask inspection tools we “don’t know what we don’t know” in terms of how bad the problem is. Cost, of course, is just as critical as performance, and a $100M tool will need at least 100 wafers per hour in production throughput (spec’ed throughput much higher) to be viable. The effort required to get beyond 100 wafers per hour is huge, especially since the exposure dose constraints that LWR will put on the resist are not likely to be overcome. We have no roadmap, let alone on upgrade path, for reducing LWR to 2 nm.

And so the final push is on. It will be an all-out effort by the industry for the next 12 – 24 months to try to make EUV lithography work. But ASML has 10 production EUV tool orders in their hands. How did they manage that, given the uncertainty involved and the fact that the preproduction tool has yet to be evaluated? As one chip maker told me, ASML is very good at “twisting arms”. Another chip maker said they had no choice but to “play the game”. After all, ASML controls the spigot on 193-nm immersion tools. So the orders are in, and the industry is sharing the risk with ASML (probably not a bad thing). If this year at the SPIE Advanced Lithography Symposium was interesting, next year promises to be even more so.

To make it clear, I am a skeptic, but I would be happy if EUV lithography was successful. I’m doing my part by trying to understand the fundamentals of LWR. Regardless of the outcome, the EUV effort is fun science and engineering! I hope we will continue to work on the hard problems of EUV in the cold light of reason.

The most pleasantly surprising aspect of this year’s symposium was the variety and quality of work presented at the Alternate Lithographic Technologies conference. Now that EUV has been separated out as its own conference, the Alternate Lithography conference has been able to flourish with exciting presentations on nanoimprint, directed self-assembly, interferometric lithography, and many other innovations. The University of Wisconsin had a great talk on modeling self-assembly. Virginia Tech surprised me with a novel (and potentially revolutionary) approach to double patterning as a non-linear double exposure. And it is always fun to think about the bizarre behavior of evanescent waves, inspired by a very good talk from the University of Canterbury (Christchurch, New Zealand).

And now I’m going home, where I hope to catch up on the sleep I’ve lost in the last week. Am I getting too old for life in the fast lane of advanced lithography?