Identifying what areas require special attention and how to deal with them in migrating designs.
Mapping from a field programmable gate array (FPGA) to an application specific IC (ASIC) is subject to some limitations. This white paper identifies some of the most common limitations in this mapping process and shows how the use of Atrenta’s GuideWareTM methodologies and SpyGlass® product family help the designer quickly identify and address these limitations.
FPGAs are a perfect platform for prototyping functionality or for handling logic, which may need to be upgraded in the field. In low volumes, they also may be the most cost-effective solution for many applications. However, in high volumes, the unit cost associated with an ASIC can be significantly more attractive. Therefore, for high volume designs, it is quite common to develop a design on an FPGA platform and, when functionality has stabilized, map that same design to an ASIC implementation.
Since considerable effort has typically been put into the design and verification phase, it is clearly desirable to use a translation from the proven FPGA implementation that is as automatic as possible. By far the best way to do this, in most cases, is to start from the source RTL description for the design and then re-map that, through synthesis, to the target ASIC library. This approach “almost” entirely solves the problem of mapping between two potentially very different target technologies.
A designer who takes these strategies into account when designing for the FPGA can be confident they will run into few problems when ready to map. Conversely, if the designer knows what limitations apply, they can identify those areas in the FPGA RTL that will require re-design before mapping. To download this paper, click here.
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