System Bits: April 28

Transistor encasing for better device performance
ECE Illinois researchers have discovered a more effective method for closing gaps in atomically small wires.

Led by Professor Joseph W. Lyding and graduate student Jae Won Do, the team reported this new transistor technology comprised of carbon nanotube wires shows promise in replacing silicon because it can operate 10 times as fast and is more flexible. However, it has an important gap to cross, they said. According to Lyding, the connection between the nanotubes is highly resistive and results in slowing the operation of the transistor down: When electrons go past that junction, they dissipate a lot of energy.

This resistance results in heat pooling at the junctions between the tubes, providing researchers with the perfect opportunity to “solder” these connections using a material that reacts with heat to deposit metal across the junctions. Once the current runs through, the deposited metal reduces the junction resistance, effectively stopping the energy loss, they explained.

Heat produced at carbon-nanotube junctions causes metallic material to deposit onto the junctions. (Source: ECE Illinois)

The problem has been finding a realizable approach to applying the heat-reactive materials, until now. In 2013, the researchers used a vacuum chamber to apply a gaseous chemical to metallize the junctions. The new technique, the subject of the new paper, takes a different route by applying a thin layer of solution, made from compounds that contain the metal needed to solder the junctions together.

This solders them together. (Source: ECE Illinois)

Do said this new technique is much simpler; it involves fewer steps and it’s more compatible to existing technology. They are achieving similar improvements to what they got from the gaseous method, only now they can experiment with the capabilities of other materials that aren’t gases. This will let them improve the transistors’ performance even more.

They believe the technique is transferable to the current manufacturing equipment silicon transistor manufacturers are using.

Changing the way we interact with computers
When clicking a mouse isn’t possible for everyone, something else is needed that’s just as good. To this end, a team of Cambridge University researchers at the Department of Engineering has developed a computer control interface that uses a combination of eye-gaze tracking and other inputs.

The team provided two major enhancements to a standalone gaze-tracking system. First, sophisticated software interprets factors such as velocity, acceleration and bearing to provide a prediction of the user’s intended target. Next, a second mode of input is employed, such as a joystick. They hope the eye-gaze tracking system can be used as an assistive technology for people with severe mobility impairment. Other applications being explored include military aviation and automotive environments where operators’ hands are engaged with controlling an aircraft or vehicle.

Cloud security reaches silicon
Given that hackers can glean a shocking amount of data about you based on the pattern in which your computer accesses its memory, and especially with the risk of attacks particularly acute in the cloud, a team of researchers in the group of MIT’s Srini Devadas, the Edwin Sibley Webster Professor in MIT’s Department of Electrical Engineering and Computer Science, proposed a method for thwarting these types of attacks by disguising memory-access patterns and are now implementing it in hardware.

The researchers propose a particular layout of a custom-built chip that would use their scheme, which is now moving into fabrication. And at the IEEE International Symposium on Field-Programmable Custom Computing Machines in May, they will describe some additional improvements to the scheme, which they’ve tested on reconfigurable chips.

The principle behind the scheme is that whenever a chip needs to fetch data from a particular memory address it should query a bunch of other addresses, too, so that a hacker can’t determine which one it’s really interested in. Naturally, this requires shipping much more data between the chip and memory than would otherwise be necessary.

According to the team, to minimize the amount of extra data needed, memory addresses are stored in a data structure known as a “tree.” A family tree is a familiar example of a tree, in which each “node” (a person’s name) is attached to only one node above it (the node representing the person’s parents) but may connect to several nodes below it (the person’s children).

Every address is randomly assigned to a path through the tree — a sequence of nodes stretching from the top of the tree to the bottom, with no backtracking. When the chip requires the data stored at a particular address, it also requests data from all the other nodes on the same path.

Read more here.

A new memory-access protocol assigns every memory address to a single path (green) through a data structure known as a tree. But a given node of the tree will often lie along multiple paths (blue). (Source: MIT)