Chip Architectures Becoming Much More Complex With Chiplets

By Ed Sperling and Ann Mutschler - 30 Jan, 2025 - Comments: 0

The migration from monolithic SoCs to chiplet-based designs is creating a confusing array of options and tradeoffs for design teams working at the leading edge, and the number of choices is only going to increase as third-party chiplets begin pouring into the market. That hasn't dampened the appetite for chiplets, however, which are deemed essential for future generations of semiconductors f... » read more

Assembly Design Rules Slowly Emerge

By Bryon Moyer - 27 Jan, 2025 - Comments: 0

Process design kits (PDKs) play an essential in ensuring that silicon technology can proceed from one generation to the next in a manner that design tools can keep up with. No such infrastructure has been needed for packaging in the past, but that's beginning to change with advanced packages. Heterogeneous assemblies are still ramping up, but their benefits are attracting new designs. “Chi... » read more

Startup Challenges In A Changing EDA World

By Brian Bailey - 13 Jan, 2025 - Comments: 0

The Electronic Design Automation (EDA) industry is a mature industry, but it's also one that is constantly changing. Each process node and packaging technology advancement places new demands and constraints on existing tools. In addition, changing design problems and paradigms transform how design teams operate, and the goals they target. For a relatively small industry, EDA requires a dispr... » read more

Testing For Thermal Issues Becomes More Difficult

By Gregory Haley - 10 Dec, 2024 - Comments: 0

Increasingly complex and heterogeneous architectures, coupled with the adoption of high-performance materials, are making it much more difficult to identify and test for thermal issues in advanced packages. For a single SoC, compressing higher functionality into a smaller area concentrates the processing and makes thermal effects more predictable. But that processing can happen anywhere in a... » read more

Metrology Advances Step Up To Sub-2nm Device Node Needs

By Laura Peters - 15 Oct, 2024 - Comments: 0

Metrology and inspection are dealing with a slew of issues tied to 3D measurements, buried defects, and higher sensitivity as device features continue to shrink to 2nm and below. This is made even more challenging due to increasing pressure to ramp new processes more quickly. Metrology tool suppliers must exceed current needs by a process node or two to ensure solutions are ready to meet tig... » read more

Ensure Reliability In Automotive ICs By Reducing Thermal Effects

By Lee Wang - 05 Aug, 2024 - Comments: 0

In the relentless pursuit of performance and miniaturization, the semiconductor industry has increasingly turned to 3D integrated circuits (3D-ICs) as a cutting-edge solution. Stacking dies in a 3D assembly offers numerous benefits, including enhanced performance, reduced power consumption, and more efficient use of space. However, this advanced technology also introduces significant thermal di... » read more

Design Flow Challenged By 3D-IC Process, Thermal Variation

By Karen Heyman - 27 Jun, 2024 - Comments: 0

3D-ICs are proving a challenge even for designers accustomed to dealing with power and performance tradeoffs, but they are considered an inevitable migration path for leading-edge designs due to the compute demands of AI and the continual shrinking of digital logic. 3D-ICs are widely viewed as the way to continue scaling beyond the limits of planar SoCs, and a way to add more heterogeneous d... » read more

Power-Aware Revolution In Automated Test For ICs

By Gregory Haley - 11 Jun, 2024 - Comments: 0

As semiconductor devices advance in complexity and sensitivity to power fluctuations, the integration of power-aware automatic test pattern generation (ATPG) is becoming indispensable for yield and the overall functionality of a chip. Unlike traditional ATPG, which generates test patterns solely to ensure device functionality, power-aware ATPG takes it a step further by meticulously consider... » read more

3D Metrology Meets Its Match In 3D Chips And Packages

By Laura Peters - 11 Jun, 2024 - Comments: 0

The pace of innovation in 3D device structures and packages is accelerating rapidly, driving the need for precise measurement and control of feature height to ensure these devices are reliable and perform as expected throughout their lifetimes. Expansion along the z axis is already well underway. One need look no further than the staircase-like 3D NAND stacks that rise like skyscrapers to p... » read more

Trouble Ahead For IC Verification

By Brian Bailey - 30 May, 2024 - Comments: 0

Verification complexity is roughly the square of design complexity, but until recently verification success rates have remained fairly consistent. That's beginning to change. There are troubling signs that verification is collapsing under the load. The first-time success rate fell (see figure 1) in the last survey conducted by Wilson Research, on behalf of Siemens EDA, in 2022. A new survey ... » read more

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tag: 3D ICs