tag: 3D ICs

Multi-Die Assemblies Complicate Parasitic Extraction
By Ann Mutschler - 12 Jun, 2025 - Comments: 0

The shift from planar designs to multi-die assemblies with complex interconnects is transforming what had become almost an afterthought in the design process into a first-order challenge. Parasitics include things like inductance, capacitance, and resistance, which have become more problematic at advanced nodes due to increasing logic density, thinner interconnects and insulators, and a spik... » read more

Addressing Stress In Heterogeneous 3D-IC Designs
By Shetha Nolke - 29 May, 2025 - Comments: 0

The benefits of 3D IC architectures are well-documented – smaller footprints, lower power, and increased performance. However, the move to heterogeneous 3D designs also introduces a host of new challenges that must be carefully navigated. As chip designers integrate multiple dies and technologies into a single 3D package, the interactions between the chip and package become increasingly co... » read more

Optimizing Data Movement
By Ann Mutschler - 29 May, 2025 - Comments: 1

Demand for new and better AI models is creating an insatiable demand for more processing power and much better data throughput, but it's also creating a slew of new challenges for which there are not always good solutions. The key here is figuring out where bottlenecks might crop up in complex chips and advanced packages. This involves a clear understanding of how much bandwidth is required ... » read more

Research Bits: May 13
By Jesse Allen - 13 May, 2025 - Comments: 0

Benchmarking 3D-IC cooling Researchers from Massachusetts Institute of Technology (MIT) and HRL Laboratories developed a specialized chip to test and validate cooling solutions for packaged chip stacks. The chip dissipates extremely high power, generating heat through the silicon layer and in localized hot spots to mimic high-performance logic chips. It then uses diodes to measure temperatu... » read more

Overlay, Critical Dimension, And Z-Height Metrology Solutions For Advanced Packaging
By Al Gamble - 08 May, 2025 - Comments: 0

The consumer’s thirst for AI-based applications is powering the ever-evolving electronics industry. Applications delivering higher levels of information in human language-like form, smarter at-home gadgets, the ability to receive a medical diagnosis without a doctor’s visit and the convenience of autonomous vehicles are among the applications powering this thirst. To better enable these app... » read more

Thermal Analysis Of 3D Stacking And BEOL Technologies
By Mohamed Naeim - 10 Apr, 2025 - Comments: 0

Thermal challenges in 3D-IC designs can cause a significant risk in meeting performance specifications. While the pace of Moore’s Law has slowed in recent years, system technology co-optimization (STCO) promises to mitigate technology scaling bottlenecks with system architecture tuning based on emerging technology offerings, including 3D technology. AI-driven inference accelerators continu... » read more

3D-IC Ecosystem Starts To Take Form
By Brian Bailey - 10 Apr, 2025 - Comments: 0

The adoption of chiplets is inevitable, but exactly when a mass migration toward this design approach will begin is yet to be determined. Nevertheless, some of the biggest technological and business-related barriers are being addressed. And while a chiplet-based design remains beyond the economic reach of many companies today, that is starting to change. Early signs of an emerging ecosystem ... » read more

Nearly Invisible: Defect Detection Below 5nm
By Gregory Haley - 08 Apr, 2025 - Comments: 0

Detecting sub-5nm defects creates huge challenges for chipmakers, challenges that have a direct impact on yield, reliability, and profitability. In addition to being smaller and harder to detect, defects are often hidden beneath intricate device structures and packaging schemes. Moreover, traditional optical and electrical probing methods, trusted for decades, are proving inadequate against ... » read more

Bold Prediction: 50% Of New HPC Chip Designs Will Be Multi-Die In 2025
By Shekhar Kapoor - 27 Feb, 2025 - Comments: 0

Monolithic chips have been the workhorses behind decades of technological advancement. But just as the industrial revolution saw workhorses replaced with more efficient and powerful machinery, the semiconductor industry is on the cusp of a similar revolution. Multi-die and chiplet-based designs — which integrate multiple specialized dies in a single package or stack integrated circuits ver... » read more

Chip Architectures Becoming Much More Complex With Chiplets
By Ed Sperling and Ann Mutschler - 30 Jan, 2025 - Comments: 0

The migration from monolithic SoCs to chiplet-based designs is creating a confusing array of options and tradeoffs for design teams working at the leading edge, and the number of choices is only going to increase as third-party chiplets begin pouring into the market. That hasn't dampened the appetite for chiplets, however, which are deemed essential for future generations of semiconductors f... » read more

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