Research Bits: May 13


Benchmarking 3D-IC cooling Researchers from Massachusetts Institute of Technology (MIT) and HRL Laboratories developed a specialized chip to test and validate cooling solutions for packaged chip stacks. The chip dissipates extremely high power, generating heat through the silicon layer and in localized hot spots to mimic high-performance logic chips. It then uses diodes to measure temperatu... » read more

Overlay, Critical Dimension, And Z-Height Metrology Solutions For Advanced Packaging


The consumer’s thirst for AI-based applications is powering the ever-evolving electronics industry. Applications delivering higher levels of information in human language-like form, smarter at-home gadgets, the ability to receive a medical diagnosis without a doctor’s visit and the convenience of autonomous vehicles are among the applications powering this thirst. To better enable these app... » read more

Thermal Analysis Of 3D Stacking And BEOL Technologies


Thermal challenges in 3D-IC designs can cause a significant risk in meeting performance specifications. While the pace of Moore’s Law has slowed in recent years, system technology co-optimization (STCO) promises to mitigate technology scaling bottlenecks with system architecture tuning based on emerging technology offerings, including 3D technology. AI-driven inference accelerators continu... » read more

3D-IC Ecosystem Starts To Take Form


The adoption of chiplets is inevitable, but exactly when a mass migration toward this design approach will begin is yet to be determined. Nevertheless, some of the biggest technological and business-related barriers are being addressed. And while a chiplet-based design remains beyond the economic reach of many companies today, that is starting to change. Early signs of an emerging ecosystem ... » read more

Nearly Invisible: Defect Detection Below 5nm


Detecting sub-5nm defects creates huge challenges for chipmakers, challenges that have a direct impact on yield, reliability, and profitability. In addition to being smaller and harder to detect, defects are often hidden beneath intricate device structures and packaging schemes. Moreover, traditional optical and electrical probing methods, trusted for decades, are proving inadequate against ... » read more

Bold Prediction: 50% Of New HPC Chip Designs Will Be Multi-Die In 2025


Monolithic chips have been the workhorses behind decades of technological advancement. But just as the industrial revolution saw workhorses replaced with more efficient and powerful machinery, the semiconductor industry is on the cusp of a similar revolution. Multi-die and chiplet-based designs — which integrate multiple specialized dies in a single package or stack integrated circuits ver... » read more

Chip Architectures Becoming Much More Complex With Chiplets


The migration from monolithic SoCs to chiplet-based designs is creating a confusing array of options and tradeoffs for design teams working at the leading edge, and the number of choices is only going to increase as third-party chiplets begin pouring into the market. That hasn't dampened the appetite for chiplets, however, which are deemed essential for future generations of semiconductors f... » read more

Assembly Design Rules Slowly Emerge


Process design kits (PDKs) play an essential in ensuring that silicon technology can proceed from one generation to the next in a manner that design tools can keep up with. No such infrastructure has been needed for packaging in the past, but that's beginning to change with advanced packages. Heterogeneous assemblies are still ramping up, but their benefits are attracting new designs. “Chi... » read more

Startup Challenges In A Changing EDA World


The Electronic Design Automation (EDA) industry is a mature industry, but it's also one that is constantly changing. Each process node and packaging technology advancement places new demands and constraints on existing tools. In addition, changing design problems and paradigms transform how design teams operate, and the goals they target. For a relatively small industry, EDA requires a dispr... » read more

Testing For Thermal Issues Becomes More Difficult


Increasingly complex and heterogeneous architectures, coupled with the adoption of high-performance materials, are making it much more difficult to identify and test for thermal issues in advanced packages. For a single SoC, compressing higher functionality into a smaller area concentrates the processing and makes thermal effects more predictable. But that processing can happen anywhere in a... » read more

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