Precision In Depth: Extraction Workflows For CFETs And Buried Power Rails


By Karen Chow, Sheetal Veronica, and Kunjesh Agashiwala In the heart of Manhattan, where land is scarce but demand is infinite, architects had to rethink the city grid. Instead of sprawling outward, they built upward with skyscrapers and carved subways below ground, inventing a “3D” city. Today’s chip designers face a similar dilemma: the two-dimensional plane of planar scaling is near... » read more

We Must Teach Chips To Feel Pain


By Guido Groeseneken When I was a doctorate student in the 1980s there was lots of wild speculation about Moore’s Law: give it another 10 years and transistors will stop getting smaller, they were saying back then. But in the end, the creativity of engineers turned out to be greater than the pessimism of the forecasters. Yet today I believe that we are close to the end of Moore’s Law.... » read more