tag: SystemC

The Secret To Good Comedy And SystemC Code Verification… Timing!
By Dave Kelf - 30 Jun, 2016 - Comments: 0

The High-Level Synthesis (HLS) of algorithmic code, usually written in SystemC, is steadily gaining ground. However, the verification of this code is still a somewhat mixed-up, ad-hoc process. The situation is improving as new techniques are applied, but it is clear that in-the-trenches evaluation of these solutions on real projects is more important right now than grand visions missing substan... » read more

Can Verification Meet In The Middle?
By Brian Bailey - 30 Jun, 2016 - Comments: 0

Since the dawn of time for the EDA industry, the classic V diagram has defined the primary design flow. On the left hand side of the V, the design is progressively refined and partitioned into smaller pieces. At the bottom of the V, verification takes over and as you travel up the right-hand side of the V, verification and integration happens until the entire design has been assembled and valid... » read more

Will Open-Source Work For Chips?
By Brian Bailey - 30 Jun, 2016 - Comments: 2

Open source is getting a second look by the semiconductor industry, driven by the high cost of design at complex nodes along with fragmentation in end markets, which increasingly means that one size or approach no longer fits all. The open source movement, as we know it today, started in the 1980s with the launch of the GNU project, which was about the time the electronic design automation (... » read more

The Secret to Reaching Rapid Verification Closure
By Ellie Burns - 16 Jun, 2016 - Comments: 0

Every design team is looking to reduce RTL verification time in order to meet aggressive schedules. Successful teams have moved their level of design abstraction up to the C++ or [gettech id="31018" comment="SystemC"] level and employ [getkc id="105" comment="high-level synthesis"] (HLS) within their design flow. By taking advantage of this high-level description, these teams also plug into int... » read more

System-Level Verification Tackles New Role
By Brian Bailey - 09 Jun, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, VP of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_name="Mentor Gr... » read more

DAC Day Three: UVM, Machine Learning And DFT Come Together
By Brian Bailey - 08 Jun, 2016 - Comments: 0

The industry and users have a love/hate relationship with UVM. It has quickly risen to become the most used verification methodology and yet at the same time it is seen as being overly complex, unwieldy and difficult to learn. The third day of DAC gets started with breakfast with Accellera to discuss UVM and what we can expect to see in the next 5 years. The discussion was led by Tom Alsop, pri... » read more

The Week In Review: IoT
By Jeff Dorsch - 03 Jun, 2016 - Comments: 0

Taiwan’s annual Computex trade show, celebrating its 35th anniversary this year, opened this week, and the Internet of Things is among the focus areas of the exhibition. Tsai Ing-wen, the new president of Taiwan, said at the opening ceremony, “The IoT era is coming strong. Taiwan must focus on the integration of hardware and software along with low-volume, high-variety manufacturing capabil... » read more

Cooperation Instead Of Competition
By Bill Neifert - 03 Jun, 2016 - Comments: 0

I spent more than 20 years working in EDA and managed to do so without ever working for one of the big three. Big EDA companies were always the competition. Oh sure, you’d partner with them strategically if you could, but always keeping in mind that little fish swimming with big fish often end up being eaten. That all changed seven months ago when ARM acquired Carbon’s technology and tea... » read more

Open Standards For Verification?
By Ann Mutschler - 01 Jun, 2016 - Comments: 0

The increasing use of verification data for analyzing and testing complex designs is raising the stakes for more standardized or interoperable database formats. While interoperability between databases in chip design is not a new idea, it has a renewed sense of urgency. It takes more time and money to verify increasingly complex chips, and more of that data needs to be used earlier in the fl... » read more

Going Open Source
By Dave Kelf - 26 May, 2016 - Comments: 2

Open Source often is thought of as an alternative to commercial software licensed using fairly typical business models. For example, variants of open source Linux supplied by companies such as Red Hat charge a subscription for support and maintenance. Maybe there is an opportunity to leverage Open Source alongside commercial EDA software to provide use model advantages and open development f... » read more

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