FOPLP Gains Traction in Advanced Semiconductor Packaging

By Gregory Haley - 21 Nov, 2024 - Comments: 0

Fan-Out Panel-Level Packaging (FOPLP) for advanced nodes, once hindered by manufacturability and yield challenges, is emerging as a promising solution to meet the industry’s demands for higher integration densities and cost efficiency. Traditionally, FOPLP has been a go-to solution for cost-sensitive applications in consumer electronics, IoT devices, and mid-tier automotive systems. Its ab... » read more

Revolutionizing IC Packaging With High-Density RDL Technology

By Curtis Zwenger - 24 Oct, 2024 - Comments: 0

The demand for high-performance devices, particularly in AI, HPC, and data centers, has surged dramatically in the ever-evolving landscape of integrated circuit technology. This demand has been further accelerated by the COVID-19 pandemic, pushing the boundaries of silicon technology to its limits. Enter Amkor’s S-SWIFT, a packaging solution designed to address these challenges and revolution... » read more

Managing EMI in High-Density Integration

By Gregory Haley - 19 Sep, 2024 - Comments: 0

The relentless drive for higher performance and increased functional integration has ushered in new challenges for managing electromagnetic interference (EMI) in densely packed mixed-signal environments. Integrating analog, RF, and digital circuits into a single system-on-chip (SoC) or advanced package requires solutions that reduce system size and improve performance. However, this tight in... » read more

Electromigration Concerns Grow In Advanced Packages

By Laura Peters - 18 Apr, 2024 - Comments: 0

The incessant demand for more speed in chips requires forcing more energy through ever-smaller devices, increasing current density and threatening long-term chip reliability. While this problem is well understood, it's becoming more difficult to contain in leading-edge designs. Of particular concern is electromigration, which is becoming more troublesome in advanced packages with multiple ch... » read more

Silicon Photonics Manufacturing Ramps Up

By Gregory Haley - 21 Mar, 2024 - Comments: 0

Circuit scaling is starting to hit a wall as the laws of physics clash with exponential increases in the volume of data, forcing chipmakers to take a much closer look at silicon photonics as a way of moving data from where it is collected to where it is processed and stored. The laws of physics are immutable. Put simply, there are limits to how fast an electron can travel through copper. The... » read more

Fan-Out Panel-Level Packaging Hurdles

By Anne Meixner - 24 Jan, 2024 - Comments: 0

Fan-out panel-level packaging (FOPLP) promises to significantly lower assembly costs over fan-out wafer-level packaging, providing the relevant processes for die placement, molding and redistribution layers (RDLs) formation can be scaled up with equivalent yield. There is still much work to be done before that happens. Until now, FOPLP has been adopted for devices that are manufactured in ve... » read more

Elimination Of Die-Pop Defect By Vacuum Reflow For Ultrathin Die With Warpage In Semiconductor Packaging Assembly

By Amkor - 18 Jan, 2024 - Comments: 0

Semiconductor die thickness is getting thinner over time due to improvement of power efficiency in advance power electronic packages. Ultrathin die with convex warpage can easily deteriorate the solder void removal process during solder reflow, leading to various packaging reliability issues. In particular, a new type of packaging defect phenomenon—die-pop—is observed. Vacuum reflow process... » read more

Many More Hurdles In Heterogeneous Integration

By Laura Peters - 18 Jan, 2024 - Comments: 0

Advanced packaging options continue to stack up in the pursuit of “More than Moore” and higher levels of integration. It has become a place where many high-density interconnects converge, and where many new and familiar problems need to be addressed. The industry’s first foray into fine-pitch multi-die packaging utilized silicon interposers with through-silicon vias (TSVs) to deliver s... » read more

Navigating Heat In Advanced Packaging

By Gregory Haley - 18 Jan, 2024 - Comments: 0

The integration of multiple heterogeneous dies in a package is pivotal for extending Moore’s Law and enhancing performance, power efficiency, and functionality, but it also is raising significant issues over how to manage the thermal load. Advanced packaging provides a way to pack more features and functions into a device, increasingly by stacking various components vertically rather than ... » read more

Plugging Gaps In The IC Supply Chain

By Anne Meixner - 09 Jan, 2024 - Comments: 0

Multiple touch points in manufacturing and packaging are exposing gaps in the data used to track different components, making it difficult to identify the source of issues that can affect yield and reliability, and opening the door to counterfeit or sub-standard parts. This involves more than just assigning a simple identifying code to a chip. At different points in a device's lifecycle, new... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?