tag: ASE

Planning For Panel-Level Fan-out
By Mark LaPedus - 21 Nov, 2019 - Comments: 0

Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging. Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes. Fan-out... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 08 Nov, 2019 - Comments: 0

Chipmakers The IC industry once had several leading-edge vendors that invested and built new fabs. But over time, the field has narrowed due to soaring costs and a dwindling customer base. In 1994, the share of semiconductor industry capital spending held by the top five companies was 25%, according to IC Insights. This meant that a number of companies invested and built new fabs during the... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 01 Nov, 2019 - Comments: 0

Chipmakers China has created a new $29 billion fund to help advance its semiconductor sector, according to reports from Bloomberg and others. Here's another report. The The U.S. and China are in the midst of a trade war. This has prompted China to accelerate its efforts to become more self-sufficient in semiconductor design and production. This includes DRAMs as well as logic/foundry. -----... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 25 Oct, 2019 - Comments: 0

Fab tools It’s been a tough period for memory. But is there now a sign of a rebound? For the September 2019 quarter, Lam Research reported revenue of $2.166 billion, and net income was $466 million, or $3.09 per diluted share on a U.S. GAAP basis. The outlook at Lam (LRCX) is a bright spot. “LRCX posted strong results and guidance, noting strength from logic and foundry in the December ... » read more

What’s The Best Advanced Packaging Option?
By Mark LaPedus - 17 Oct, 2019 - Comments: 2

As traditional chip designs become more unwieldy and expensive at each node, many IC vendors are exploring or pursuing alternative approaches using advanced packaging. The problem is there are too many advanced packaging options on the table already, and the list continues to grow. Moreover, each option has several tradeoffs and challenges, and all of them are still relatively expensive. ... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 04 Oct, 2019 - Comments: 0

Packaging and test In a major deal that has some implications in the OSAT supply chain, South Korea’s Nepes has taken over Deca Technologies’ wafer-level packaging manufacturing line in the Philippines. In addition, Nepes has also licensed Deca’s M-Series wafer-level packaging technology. This includes fan-in technology as well as wafer- and panel-level fan-out. It also includes an ad... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 27 Sep, 2019 - Comments: 0

Chipmakers United Microelectronics Corp. (UMC) has satisfied all closing conditions for the full acquisition of Mie Fujitsu Semiconductor Ltd. (MIFS), the former 300mm wafer foundry joint venture between UMC and Fujitsu Semiconductor Ltd. (FSL). The completion of the acquisition is scheduled for Oct. 1. In 2014, FSL and UMC agreed for UMC to acquire a 15.9% stake in MIFS from FSL through pr... » read more

The Race To Next-Gen 2.5D/3D Packages
By Mark LaPedus - 23 Sep, 2019 - Comments: 4

Several companies are racing each other to develop a new class of 2.5D and 3D packages based on various next-generation interconnect technologies. Intel, TSMC and others are exploring or developing future packages based on one emerging interconnect scheme, called copper-to-copper hybrid bonding. This technology provides a way to stack advanced dies using copper connections at the chip level,... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 20 Sep, 2019 - Comments: 0

Fab tools The confidence level of extreme ultraviolet (EUV) lithography continues to grow as the technology moves into production, but the EUV mask infrastructure remains a mixed picture, according to new surveys released by the eBeam Initiative. D2S has developed new hardware and software that enables a long-awaited technology--full-chip masks using inverse lithography technology (ILT). ... » read more

Test On New Technology’s Frontiers
By SE Staff - 10 Sep, 2019 - Comments: 2

Semiconductor testing is getting more complicated, more time-consuming, and increasingly it requires new approaches that have not been fully proven because the technologies they are addressing are so new. Several significant shifts are underway that make achieving full test coverage much more difficult and confidence in the outcome less certain. Among them: Devices are more connected an... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy