Chip Architectures Becoming Much More Complex With Chiplets
Options for how to build systems increase, but so do integration issues.
Chiplets Still A Challenge With UCIe 2.0
New connectivity standard brings performance improvements and a bunch of new features, but it may take years before they are adopted — and still may not result in an open chiplet market.
Chip Industry Week In Review
Critical IC mineral concerns; wafer shipments shrink; Europe bets big on AI; new ultrasonic cleaner; high-speed DRAM test; Europe's 6G; HW-assisted verification; India IC grows; NPU acquisition; power spikes in AI workloads.
Shift Left Is The Tip Of The Iceberg
A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.
NAND Flash Targets 1,000 Layers
New techniques go beyond improved deposition and etching, but challenges stack up, too.
Testing For Thermal Issues Becomes More Difficult
Chiplets, exotic materials, and heterogeneous integration are impacting test coverage.
Auto Chip Aging Accelerates In Hot Climates
New data shows significant reduction in lifespan and potential new security issues as global temperatures rise.
Is In-Memory Compute Still Alive?
It hasn’t achieved commercial success, but there is still plenty of development happening; analog IMC is getting a second chance.
Hybrid Bonding Makes Strides Toward Manufacturability
Companies are selecting preferred flows, but the process details are changing rapidly to meet the needs of different applications.
Baby Steps Toward 3D DRAM
Stacking layers means a complete architecture rethink.
