Detecting Architectural Vulnerabilities in Closed-Source RISC-V CPUs (CISPA)


The paper "RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs" was published by researchers at CISPA Helmholtz Center for Information Security. Abstract "The open and extensible RISC-V instruction set has enabled many new CPU vendors and implementations, but most commercial CPUs are closed-source, significantly hindering vul... » read more

Security Technical Paper Roundup: Sept. 30


A number of hardware security-related technical papers were presented at the August 2025 USENIX Security Symposium. The organization provides open access research, and the presentation slides and papers are free to the public. Topics include side-channel attacks and defenses, embedded security, fuzzing, fault injection, rowhammer, and more. Here are some highlights with associated links: [ta... » read more

CPU Fuzzing Via Intricate Program Generation (ETH Zurich)


A technical paper titled “Cascade: CPU Fuzzing via Intricate Program Generation” was published by researchers at ETH Zurich. Abstract: "Generating interesting test cases for CPU fuzzing is akin to generating programs that exercise unusual states inside the CPU. The performance of CPU fuzzing is heavily influenced by the quality of these programs and by the overhead of bug detection. Our a... » read more