Chip Industry Week In Review


Siemens announced plans to acquire Altair Engineering, a provider of industrial simulation and analysis, data science, and high-performance computing (HPC) software, for about $10 billion. Altair's software will become part of Siemens' Xcelerator portfolio and provide a boost to physics-based digital twins. Onto Innovation bought Lumina Instruments, a San Jose, California-based maker of lase... » read more

Chip Industry Week In Review


By Susan Rambo, Gregory Haley, and Liz Allan Amkor plans to invest about $2 billion in a new advanced packaging and test facility in Peoria, Arizona. When finished, it will employ about 2,000 people and will be the largest outsourced advanced packaging facility in the U.S. The first phase of the construction is expected to be completed and operational within two to three years. Synopsys p... » read more

Chip Industry Week In Review


By Jesse Allen, Susan Rambo, and Liz Allan The U.S. government will invest about $3 billion for the National Advanced Packaging Manufacturing Program (NAPMP), including an advanced packaging piloting facility to help U.S. manufacturers adopt new technology and workforce training programs. It also will provide funding for projects concentrating on materials and substrates; equipment, tools, ... » read more

Chip Industry Week In Review


By Susan Rambo, Gregory Haley, Jesse Allen, and Liz Allan President Biden issued an executive order on the “Safe, Secure, and Trustworthy Development and Use of Artificial Intelligence.” It says entities need to report large-scale computing clusters and the total computing power available, including “any model that was trained using a quantity of computing power greater than 1,026 inte... » read more

Week In Review: Manufacturing, Test


TSMC, Bosch, Infineon, and NXP will jointly invest in the European Semiconductor Manufacturing Co. (ESMC), in Dresden, Germany, to provide advanced semiconductor manufacturing services. ESMC marks a significant step toward construction of a 300mm fab, which is expected to have a monthly production capacity of 40,000 300mm (12-inch) wafers on TSMC’s 28/22nm planar CMOS and 16/12nm finFET proce... » read more

Multiple Hurdles In The Race To 6G


The rollout of 6G will open the door to significant changes and possibilities, but whether this technology lives up to the hype will require massive collaborative efforts, huge investments in infrastructure, and solving some problems for which there are no precedents. Multiple companies are already working on 6G technology, aiming for a maximum download speed of one terabit per second (Tb/s)... » read more

Week In Review: Auto, Security, Pervasive Computing


Inflection AI raised $1.3 billion in a new funding round led by Microsoft, Reid Hoffman, Bill Gates, Eric Schmidt, and NVIDIA after raising $225 million in the first round to support the ongoing development of Pi, a “useful, friendly, and fun” AI. In partnership with CoreWeave and NVIDIA, Inflection aims to build the world’s largest AI cluster, comprised of 22,000 NVIDIA H100 Tensor Core ... » read more

Chips Can Boost Malware Immunity


Security is becoming an increasingly important design element, fueled by increasingly sophisticated attacks, the growing use of technology in safety-critical applications, and the rising value of data nearly everywhere. Hackers can unlock automobiles, phones, and smart locks by exploiting system design soft spots. They even can hack some mobile phones through always-on circuits when they are... » read more

Increasing Performance With Data Acceleration


Increasing demand for functions that require a relatively high level of acceleration per unit of data is providing a foothold for in-line accelerator cards, which could mean new opportunities for some vendors and a potential threat for others. For years, either CPUs, or CPUs with FPGA accelerators, met most market needs. But the rapid increase in the volume of data everywhere, coupled with t... » read more

Week In Review: Design, Low Power


Tools & IP Imperas Software introduced the RISC-V Verification Interface (RVVI). The open standard and methodology can be adapted to any configuration permitted within the RISC-V specifications. RVVI defines interfaces between RTL, reference model, and testbench for RISC-V design verification, with the aim of making RISC-V processor DV reusable. It supports multi-hart, superscalar, and out... » read more

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