tag: design for yield

Industry Scorecard For 2014
By Brian Bailey - 22 Dec, 2014 - Comments: 0

At the end of last year, Semiconductor Engineering asked the industry about the developments they expected to see in 2014. If you care to refresh your memory, they were categorized under markets, semiconductors and development tools. Now it is time to look back and see how accurate those predictions were and where they fell short. Part one addressed the market and semiconductor areas and in thi... » read more

Root Cause Deconvolution
By Mentor, a Siemens Business - 19 Jun, 2014 - Comments: 0

Scan logic diagnosis turns failing test cycles into valuable data and is an established method for digital semiconductor defect localization. The advent of layout-aware scan diagnosis represented a dramatic advance in diagnosis technology because it reduces suspect area by up to 85% and identifies physical net segments rather than entire logic nets [1-3]. The defect classifications provided by ... » read more

The Road Ahead For 2014: Tools
By Brian Bailey - 30 Jan, 2014 - Comments: 0

In the third and final part of this predictions series we see the natural conclusion of market shifts that are driving changes in semiconductors, and which in turn drive the tools and IP needed to create those systems. To be expected, the changes fall into a few areas: New tools, techniques and changes required for smaller geometries; A migration to higher-levels of abstraction and the... » read more

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