The Week In Review: Design

By Jesse Allen - 31 Mar, 2017 - Comments: 0

M&A Siemens closed the acquisition of Mentor Graphics, making Mentor now part of Siemens' product lifecycle management (PLM) software business. The $4.5 billion deal, announced last November, brings Siemens into the IC design tool and embedded software markets and expands Siemens' multi-physics and electronic simulation capabilities in the growing digital twin space, which ties together ... » read more

Blog Review: March 29

By Jesse Allen - 29 Mar, 2017 - Comments: 0

In a video, Cadence's Megha Daga introduces how convolutional neural networks identify objects and the wide range of applications for the technology. Mentor's Ron Press proposes a way to take advantage of hierarchical DFT features, even if a design wasn't designed for it. Synopsys' Robert Vamosi shares highlights of the RAND Corporation's extensive report examining zero day vulnerabilitie... » read more

The Week In Review: Design

By Jesse Allen - 19 Aug, 2016 - Comments: 0

Tools Aldec uncorked its TySOM embedded development kit, which includes Riviera-PRO mixed-HDL language simulation for VHDL 2008/Verilog 2005, a Xilinx Zynq-based development board and pre-validated Ubuntu Embedded Host reference designs and tutorials. Mentor Graphics introduced the first phase of its new Xpedition PCB design flow with technologies for design and verification of rigid and ... » read more

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Intel Vs. Samsung Vs. TSMC

Foundry competition heats up in three dimensions and with novel technologies as planar scaling benefits diminish.

by Ed Sperling

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Chip Industry Week In Review

Softbank's acquisition; advanced packaging funding; glass substrates; engineered copper wire; semi equipment set new record; HBM4; AI chips rake in funding; X-ray inspection; apprenticeships.

by The SE Staff

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

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The Week In Review: Design

Blog Review: March 29

The Week In Review: Design

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