Week In Review: Manufacturing, Test

By Mark LaPedus - 21 Jan, 2022 - Comments: 0

Fabs Intel has announced plans for an initial investment of more than $20 billion in the construction of two new leading-edge fabs in Ohio. Planning for the first two factories will start immediately, with construction expected to begin late in 2022. Production is expected to come online in 2025. As part of the announcement, Air Products, Applied Materials, Lam Research and Ultra Clean Technol... » read more

Benefits Of Multilevel Topologies In Power-Efficient Energy Storage Systems (ESS)

By Infineon - 07 Apr, 2021 - Comments: 0

In this paper, we discuss the adaption of efficient energy storage systems (ESS) in residential solar and utility-scale applications. System requirements and possible topologies are looked into. For utility-scale, we introduce a multilevel converter topology concept. Click here to read more. » read more

Manufacturing Bits: Oct. 4

By Mark LaPedus - 04 Oct, 2016 - Comments: 0

China’s powerful laser The Shanghai Superintense-Ultrafast Lasers Facility (SULF) in China claims to have demonstrated the world’s most powerful laser. The ultra-intense, ultra-fast laser is said to have delivered a peak power of more than five petawatts. This is supposedly the largest peak-power laser pulse ever measured on record. A petawatt is equivalent to one quadrillion watts. ... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: ESS

Week In Review: Manufacturing, Test

Benefits Of Multilevel Topologies In Power-Efficient Energy Storage Systems (ESS)

Manufacturing Bits: Oct. 4