tag: Galois

Week In Review: Design, Low Power
By Jesse Allen - 12 Mar, 2021 - Comments: 0

Tools & IP Codasip unveiled three commercially licensed add-ons to the Western Digital SweRV Core EH1, aiming to allow it to be designed into a wider range of applications. The SweRV Core EH1 is a 32-bit, dual-issue, RISC-V ISA core with a 9-stage pipeline, open-sourced through CHIPS Alliance. The add-ons offer a floating-point unit (FPU) that supports the RISC-V single precision [F] and d... » read more

Why It’s So Hard To Stop Cyber Attacks On ICs
By Ed Sperling - 23 Dec, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss security risks across multiple market segments with Helena Handschuh, security technologies fellow at Rambus; Mike Borza, principal security technologist for the Solutions Group at Synopsys; Steve Carlson, director of aerospace and defense solutions at Cadence; Alric Althoff, senior hardware security engineer at Tortuga Logic; and Joe Kiniry, princi... » read more

Security Gaps In Open Source Hardware And AI
By Ed Sperling - 25 Nov, 2020 - Comments: 1

Semiconductor Engineering sat down to discuss security risks across multiple market segments with Helena Handschuh, security technologies fellow at Rambus; Mike Borza, principal security technologist for the Solutions Group at Synopsys; Steve Carlson, director of aerospace and defense solutions at Cadence; Alric Althoff, senior hardware security engineer at Tortuga Logic; and Joe Kiniry, princi... » read more

Dealing With Security Holes In Chips
By Ed Sperling - 05 Nov, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss security risks across multiple market segments with Helena Handschuh, security technologies fellow at Rambus; Mike Borza, principal security technologist for the Solutions Group at Synopsys; Steve Carlson, director of aerospace and defense solutions at Cadence; Alric Althoff, senior hardware security engineer at Tortuga Logic; and Joe Kiniry, princi... » read more

The Evolution Of High-Level Synthesis
By Brian Bailey - 27 Aug, 2020 - Comments: 3

High-level synthesis is getting yet another chance to shine, this time from new markets and new technology nodes. But it's still unclear how fully this technology will be used. Despite gains, it remains unlikely to replace the incumbent RTL design methodology for most of the chip, as originally expected. Seen as the foundational technology for the next generation of EDA companies around the ... » read more

Week in Review: IoT, Security, Auto
By Jeff Dorsch - 10 May, 2019 - Comments: 0

Internet of Things Microsoft this week introduced IoT Plug and Play, a no-code toolkit for connecting Internet of Things devices to the cloud. The company touts it as a new modeling language to pump up the capabilities of IoT devices through the Microsoft Azure cloud service. The Azure IoT Device Catalog lists devices that support IoT Plug and Play, such as the STMicroelectronics SensorTile.bo... » read more

Building Security Into RISC-V Systems
By Ed Sperling - 30 Jan, 2019 - Comments: 0

Semiconductor Engineering sat down with Helena Handschuh, a Rambus fellow; Richard Newell, senior principal product architect at Microsemi, a Microchip Company; and Joseph Kiniry, principal scientist at Galois. Part one is here. (This is the second of two parts.) L-R: Joseph Kiniry, Helena Handschuh, Richard Newell. SE: Some of the new applications for hardware designs are tied to AI, d... » read more

Open-Source RISC-V Hardware And Security
By Ed Sperling - 12 Dec, 2018 - Comments: 0

Semiconductor Engineering sat down with Helena Handschuh, a Rambus fellow; Richard Newell, senior principal product architect at Microsemi, a Microchip Company; and Joseph Kiniry, principal scientist at Galois. What follows are excerpts of that conversation. (L-R) Joseph Kiniry, Helena Handschuh and Richard Newell. SE: Is open-source hardware more secure, or does it just open up vulnera... » read more

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