Get To Know The Gate-Level Power Aware Simulation

The post-synthesis gate-level netlist (GL-netlist) based PA simulation input requirements are mostly the same as RTL simulation. However, the design under verification here is the GL-netlist from synthesis, so logic gates from standard, MV and Macro cell Liberty libraries are already inserted or instantiated in the design. Hence power aware simulation (PA-SIM) at post-synthesis also requires Li... » read more