The Week In Review: Design

By Jesse Allen - 27 May, 2016 - Comments: 0

Mergers & Acquisitions Synopsys made a couple of announcements this week related to its TCAD business. First, they acquired Gold Standard Simulations, which clearly became a major factor in the release of a pre-wafer simulation solution to help semiconductor manufacturers reduce process node development time. The new solution aims to provide a comprehensive process, transistor and circui... » read more

Synopsys Buys Gold Standard Simulations

By Brian Bailey - 23 May, 2016 - Comments: 1

[getentity id="22035" e_name="Synopsys"] has made another quiet acquisition, this time in the TCAD space. [getentity id="22272" comment="Gold Standard Simulations (GSS)"] offers a suite of solutions for design technology co-optimization (DTCO), PDK development and exploration and screening of future technology options. Their tool chain integrates predictive Monte Carlo and statistical TCAD s... » read more

Scaling The Lowly SRAM

By Mark LaPedus - 05 Jun, 2013 - Comments: 0

By Mark LaPedus Chipmakers face a multitude of challenges at the 20nm logic node and beyond, including the task of cramming more functions on the same chip without compromising on power and performance. There is one major challenge that is often overlooked in the equation—scaling the lowly static RAM (SRAM). In one key application, SRAM is the component used to make on-chip cache memories... » read more

Multicore Madness

By Mark LaPedus - 21 Feb, 2013 - Comments: 0

By Mark LaPedus Smartphones and tablets are migrating towards new and faster application processors, basebands, graphics chips and memories. In the cell-phone chipset area alone, there are a multitude of options and design considerations. Some devices combine the application processor and modem on the same chip. Some are separate devices. In addition, the architectures range from single- to... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Gold Standard Simulations

The Week In Review: Design

Synopsys Buys Gold Standard Simulations

Scaling The Lowly SRAM

Multicore Madness