tag: hierarchical verification

Efficient Hierarchical Verification For Low Power Designs

By Susantha Wijesekara - 17 Jan, 2019 - Comments: 0

By Susantha Wijesekara and Himanshu Bhatt Growing design sizes, low power (LP) complexity and the need for early stage verification is making designers adopt hierarchical verification flows. Traditionally for hierarchical verification, designers use a black box, liberty model based hierarchical flow, timing model (ETM) flow or stub/glass box flows that offer various degrees of trade-offs for... » read more

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