NoC Coherency Challenges Balloon With AI SoCs And Chiplets


Key Takeaways Data movement, congestion, and energy efficiency are key determiners of whether compute is usable. Different processors bring various coherency challenges. For example, a cache-coherent NoC for CPUs is expensive and harder to verify than an I/O-coherent NoC for an accelerator. Designers need to balance top-down performance with bottom-up physical engineering to effect... » read more

An Entangled Heterarchy


For decades, a form of structural hierarchy has been the principal means of handling complexity in chip design. It's not always perfect, and there is no ideal way in which to divide and conquer because that would need to focus on the analysis being performed. In fact, most systems can be viewed from a variety of different hierarchies, equally correct, and together forming a heterarchy. The e... » read more

Hierarchy And Pain Management


By Bernard Murphy Hierarchy is unavoidable for any large design. It partitions development and verification complexity into digestible chunks. It enables parallel development on different parts of a system. It promotes reuse. And it provides a graceful method to partition for implementation. And yet, there are times when hierarchy gets in the way. The biggest drawback with hierarchy is that... » read more