tag: Keysight

Chip Aging Opens Up New Attack Vectors
By Adam Kovac - 03 Apr, 2025 - Comments: 0

The longer a piece of silicon is out in the field the more prone it becomes to a cyberattack, raising questions about the optimal longevity of circuits and the impact of extending their lifetimes. This is particularly challenging for safety- and mission-critical applications, where the cost of development can run as high as $100 million for some of the most complex designs. Chipmakers want t... » read more

Blog Review: Apr. 2
By Jesse Allen - 02 Apr, 2025 - Comments: 0

Synopsys’ Meenakshy Ramachandran explores how DisplayPort Automotive Extensions help meet functional safety and security standards for the increasingly higher-resolution and more immersive in-vehicle displays in connected, autonomous, shared, and electric vehicles. Siemens’ Gabriella Leone and Michael Munsey discuss the need for a collaborative semiconductor business platform and how to ... » read more

Chip Industry Week In Review
By The SE Staff - 28 Mar, 2025 - Comments: 0

McKinsey issued a new report on the state of the chemical supply chain for semiconductors in the U.S., citing potential shortages of high-purity materials such as tungsten, aluminum and copper, lack of access to CMP slurries and photoresists for EUV, and rising competition for high-k precursors that can fetch higher prices outside of the U.S. CSIS weighed in on the U.S. goverment's recent ... » read more

Innovating For 6G
By Hwee Yng Yeo - 27 Mar, 2025 - Comments: 0

As the world eagerly anticipates the arrival of applicable 6G innovations, researchers face numerous challenges in validating this next-generation wireless communication technology. The journey from theoretical concepts and mathematical equations to real-world 6G implementation is complex and requires meticulous planning, testing, and measurements to better characterize these ultra-high freque... » read more

Challenges In Managing Chiplet Resources
By Ann Mutschler - 27 Mar, 2025 - Comments: 0

Managing chiplet resources is emerging as a significant and multi-faceted challenge as chiplets expand beyond the proprietary designs of large chipmakers and interact with other elements in a package or system. Poor resource management in chiplets adds an entirely new dimension to the usual power, performance, and area tradeoffs. It can lead to performance bottlenecks, because as chiplets co... » read more

Dynamic Characterization Of A Power Semiconductor Bare Chip
By Keysight - 26 Mar, 2025 - Comments: 0

Power semiconductor devices are used in a variety of forms, such as being packaged in Surface Mount Devices (SMDs) or power modules, and they find broad applications. Power semiconductor bare chips are loaded into these packages. It is desirable to characterize the bare chip before placing it in a package or a power module to expedite development. However, the small size, fragile structure, and... » read more

Blog Review: Mar. 26
By Jesse Allen - 26 Mar, 2025 - Comments: 0

Siemens' Bianca Ward argues that sustainability must be considered starting from the design phase to reduce the energy consumption of ICs as well as the production processes used to manufacture them. Synopsys' Adrien Tozzoli looks at how physical optics simulation can be improved by using beam synthesis propagation, a method that decomposes the optical field into a collection of beamlets to ... » read more

Chip Industry Week In Review
By The SE Staff - 21 Mar, 2025 - Comments: 0

Semiconductor industry energy consumption grew 125% between 2015 and 2023, while direct greenhouse gas emissions rose 23% in the same period, according to the Europe think tank Interface, which analyzed corporate social responsibility reports from 28 global chip manufacturers. CSIS' new report "Understanding U.S. Allies’ Current Legal Authority to Implement AI and Semiconductor Export Cont... » read more

Blog Review: Mar. 19
By Jesse Allen - 19 Mar, 2025 - Comments: 0

Cadence's Neelabh Singh explains the defined port operations of USB4 that are used to bring transmitters burst and receivers of a design under test into compliance mode and to execute tests like bit error tests, error rate tests, clock switch tests, TxFFE equalization tests, and electrical idle tests. Siemens EDA's Stephen V. Chavez examines the use of blind and buried vias in high-density i... » read more

Integrating Data From Design, Manufacturing, And The Field
By Adam Kovac - 13 Mar, 2025 - Comments: 0

Chip design is starting to include more options to ensure chips behave reliably in the field, boosting the ability to tweak both hardware and software as chips age. The basic problem is that as dimensions become smaller, and as more features are added into devices — especially with heterogeneous assemblies of chiplets running some type of AI — the potential for thermally induced structur... » read more

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