tag: locking optimization

Synchronization Overview And Case Study on Arm Architecture

By Arm - 10 Aug, 2022 - Comments: 0

The objective of this white paper is to share knowledge on Arm architecture. The target reader of this document is those who work on synchronization with the Arm architecture. [Warning] When we are dealing with locking optimizations, we must be extremely careful about correctness. Bugs caused by synchronization are usually hard to root cause and the optimized code may crash on other CPUs wit... » read more

Trending Articles

Chip Industry Week In Review

Applied Materials' $4B facility at risk; AI chip bonanza; Japan, U.S. alliance; Rapidus' U.S. subsidiary; EDA revenue up; TSMC $6.6B funding; Infineon, Amkor team up; S. Korea's big bet; Apple's processor overhaul; high-NA EUVL defect system; chiplet HW security module; new Spectre attack.

by The SE Staff

Chip Industry Week In Review

China restricts U.S. processors; Samsung's CXL, DRAM module and roadmap; ASML's $2.7B retention bonus; U.S., Mexico partner up; Keysight's $1.5B offer to Spirent; Lam's new pulsed laser deposition; new OSAT center.

by The SE Staff

Architecting Chips For High-Performance Computing

Data center IC designs are evolving, based on workloads, but making the tradeoffs for those workloads is not always straightforward.

by Ann Mutschler

Early STEM Education Key To Growing Future Chip Workforce

Community outreach and partnerships can drive interest in STEM subjects and chip jobs among children, parents, and teachers.

What Works Best For Chiplets

Not all chiplets are interchangeable, and options will be limited.

by Anne Meixner

Knowledge Centers
Entities, people and technologies explored

Related Articles

The Rising Price Of Power In Chips

More data requires faster processing, which leads to a whole bunch of problems — not all of which are obvious or even solvable.

by Ed Sperling

The Future Of Memory

From attempts to resolve thermal and power issues to the roles of CXL and UCIe, the future holds a number of opportunities for memory.

by Karen Heyman

SRAM Scaling Issues, And What Comes Next

While it will remain a workhorse memory, using SRAM at advanced nodes requires new approaches.

by Karen Heyman

Verifying Hardware Security With RTL Simulation

Measuring how injected faults propagate through a design and how long they remain in the system.

by Taruna Reddy

Backside Power Delivery Adds New Thermal Concerns

Lack of shielding, routing issues, and new mechanical stresses could have broad impact on standard cell design.

by Karen Heyman

Architecting Chips For High-Performance Computing

Data center IC designs are evolving, based on workloads, but making the tradeoffs for those workloads is not always straightforward.

by Ann Mutschler

Glitch Power Issues Grow At Advanced Nodes

Problem is particularly acute in AI accelerators, and fixes require some complex tradeoffs.

by Ann Mutschler

Rethinking Memory

Von Neumann architecture is here to stay, but AI novel architectures and 3D structures create a need for new testing tools.

by Karen Heyman

About

Navigation

Connect With Us

Facebook
Twitter @semiEngineering
LinkedIn
YouTube

Copyright ©2013-2024 SMG | Terms of Service | Privacy Policy