How To Cut Verification Costs For IoT

By Brian Bailey - 25 Sep, 2014 - Comments: 0

Cost is one of the main factors limiting proliferation of the [getkc id="76" comment="Internet of Things"] (IoT), and when looking at the design and [getkc id="10" kc_name="Verification"] methodologies in place today, verification is a prime candidate for closer inspection. For today’s complex [getkc id="81" kc_name="SoCs"], the cost of verification has been rising faster than design and it h... » read more

Fixing Functional Coverage

By Brian Bailey - 22 Aug, 2014 - Comments: 2

Constrained random test pattern generation entered the scene a couple of decades ago as a better way to spend time and resources for the creation of stimulus. Stimulus definition had become an arduous task—defining the patterns necessary to exercise designs of increasing size. It was successfully argued that spending time writing models instead of creating stimulus and having a computer p... » read more

Looking For The Next Big Thing

By Brian Bailey - 21 Aug, 2014 - Comments: 0

With [getkc id="74" comment="Moore's Law"] slowing down or coming to an end, finding the next big thing may be very different than it was in the past. We cannot assume that more of the same will be a winner. The semiconductor industry has been blessed with two new product categories that have catapulted it through what should have been a very difficult period with barely a scratch. Those techno... » read more

Is Formal Ready To Displace Simulation?

By Brian Bailey - 21 May, 2014 - Comments: 2

In part one of this roundtable, the panelists talked about the recent changes that have brought formal to the forefront of verification and discussed the challenges that the UVM have brought to formal. In part two, the panel focused on the subject of coverage and the ways in which formal coverage can be combined with simulation. In this segment we start exploring the impact that sequential equi... » read more

Does Formal Have You Covered?

By Brian Bailey - 24 Apr, 2014 - Comments: 1

In part one of this roundtable, the panelists talked about the recent changes that have brought formal to the forefront of verification and discussed the challenges that the UVM have brought to formal. In this segment we start exploring those difficulties in more detail and the progress made with integrated coverage. Participating in the panel were Pete Hardee, director of product management fo... » read more

Formal Is Set To Overtake Simulation

By Brian Bailey - 27 Mar, 2014 - Comments: 4

There has been a significant psychology change in the area of formal verification over the past couple of years. It’s no longer considered a fringe technology, and it’s no longer considered difficult to use. In fact, it has become a necessary part of the verification process. Semiconductor Engineering sat down with a panel of experts to find out what caused this change and what more we c... » read more

The Road Ahead For 2014: Tools

By Brian Bailey - 30 Jan, 2014 - Comments: 0

In the third and final part of this predictions series we see the natural conclusion of market shifts that are driving changes in semiconductors, and which in turn drive the tools and IP needed to create those systems. To be expected, the changes fall into a few areas: New tools, techniques and changes required for smaller geometries; A migration to higher-levels of abstraction and the... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer