tag: physical effects

Higher Density, More Data Create New Bottlenecks In AI Chips
By Adam Kovac - 12 Sep, 2024 - Comments: 0

Data movement is becoming a bigger problem at advanced nodes and in advanced packaging due to denser circuitry, more physical effects that can affect the integrity of signals or the devices themselves, and a significant increase in data from AI and machine learning. Just shrinking features in a design is no longer sufficient, given the scaling mismatch between SRAM-based L1 cache and digital... » read more

The Rising Price Of Power In Chips
By Ed Sperling - 14 Mar, 2024 - Comments: 0

Power is everything when it comes to processing and storing data, and much of it isn't good. Power-related issues, particularly heat, dominate chip and system designs today, and those issues are widening and multiplying. Transistor density has reached a point where these tiny digital switches are generating more heat than can be removed through traditional means. That may sound manageable e... » read more

Speeding Up Design Closure
By Ed Sperling - 23 Aug, 2023 - Comments: 0

Increasing complexity and smaller process nodes make it far more difficult to achieve design closure for chips. There are more physical effects to model, including noise, cross-talk, and double switching effects, all of which can slow the design process. Solaiman Rahim, vice president of engineering for Synopsys’ EDA Group, talks about why it’s so important to analyze violations in design, ... » read more

The Everything New Syndrome
By Ed Sperling - 12 Oct, 2021 - Comments: 0

Technology is all about the latest features, the fastest processing, with the lowest power. While that sounds great in marketing pitch, any or all of those factors don't necessarily equate to a better product or long-term user satisfaction. There's a reason semiconductor companies are conservative by nature. They want to know that when they spend tens or hundreds of millions of dollars on a ... » read more

What’s Changing In DRAM
By Ed Sperling - 15 Sep, 2021 - Comments: 0

Most of the attention in chip scaling has been focused on logic and on-chip memory, but off-chip memory is starting to encounter problems, as well. David Fried, vice president of computational products at Lam Research, looks at the impact of shrinking features and increasing density, including variation, thermal effects and aging, as well as effects such as micro-loading and DRAM stacking. » read more

Reliability Over Time And Space
By Ed Sperling - 13 Oct, 2020 - Comments: 0

The demand for known good die is well understood as multi-chip packages are used in safety-critical and mission-critical applications, but that alone isn't sufficient. As chips are swapped in and out of packages to customize them for specific applications, it will be the entire module that needs to be verified, simulated and tested, and analyzed. This is more complicated than it sounds for s... » read more

Preparing For A Barrage Of Physical Effects
By Ann Mutschler - 13 Aug, 2020 - Comments: 0

Advancements in 3D transistors and packaging continue to enable better power and performance in a given footprint, but they also require more attention to physical effects stemming from both increased density and vertical stacking. Even in planar chips developed at 3nm, it will be more difficult to build both thin and thick oxide devices, which will have an impact on everything from power to... » read more

Improving Circuit Reliability
By Ed Sperling - 03 Mar, 2020 - Comments: 0

Carey Robertson, product marketing director at Mentor, a Siemens Business, examines reliability at advanced and mainstream nodes, particularly in automotive and industrial applications, what’s driving growing concern about the reliability and fidelity of analog circuits, and the impact of running circuits for longer periods of time under different voltage and environmental conditions. » read more

Rethinking Memory
By Ed Sperling - 16 Dec, 2015 - Comments: 3

Getting data in and out of memory is as important as the speed and efficiency of a processor, but for years design teams managed to skirt the issue because it was quicker, easier and less expensive to boost processor clock frequencies with a brute-force approach. That worked well enough prior to 90nm, and adding more cores at lower clock speeds filled the gap starting at 65nm. After that, th... » read more

Pain Management
By Ed Sperling - 10 Apr, 2014 - Comments: 0

In part one of this series, the focus was on overlapping and new pain points in the semiconductor flow, from initial conception of what needs to be in a chip all the way through to manufacturing. Part two looks at how companies are attempting to manage that pain. It’s no secret that [getkc id="81" kc_name="SoC"]s are getting more complicated to design, debug and build, but the complexity i... » read more

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