tag: physical IP

Trimming Waste In Chips
By Brian Bailey - 12 Oct, 2017 - Comments: 0

Extra circuitry costs money, reduces performance and increases power consumption. But how much can really be trimmed? When people are asked that question they either get defensive or they see it as an opportunity to show the advantages of their architecture, design process or IP. The same holds true for IP suppliers. Others point out that the whole concept of waste is somewhat strange, becau... » read more

A Broad, Effective Approach to Optimizing for Power
By Wolfgang Helfricht - 15 Jul, 2015 - Comments: 0

As an industry we talk a lot about the challenges of power-aware design and accompanying issues at leading-edge nodes. There’s no denying some tough challenges, but if we’re honest, there are plenty of opportunities we can exploit right now to improve power in our designs. You’ve heard the saying, “death by a thousand cuts?” Well, when it comes to grappling with power in today’s ... » read more

FinFET Impacts For Reducing Physical IP Power Consumption
By Navraj Nandra - 07 Nov, 2013 - Comments: 0

FinFET devices were developed to address the need for improved gate control to suppress leakage current (IOFF); DIBL (drain-induced barrier lowering); and process‐induced variability below 32-nanometer. FinFET technology is now in volume production. To fully realize the advantages of FinFET devices, physical IP must follow the same trajectory that has benefited digital design. That include... » read more

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy