tag: Portable Stimulus Working Group

Reflecting Back On 2016
By Brian Bailey - 22 Dec, 2016 - Comments: 0

Anyone can make a prediction, and sometimes the more outlandish they are the more they get noticed. But at the end of the year some people hit the mark while others may have been way off. Many people simply make projections based on the current trajectory of trends, while others look for the potential discontinuities that may lie ahead. Semiconductor Engineering examines the projections made... » read more

Verification Specialists And Generalists
By Dave Kelf - 22 Nov, 2016 - Comments: 0

Step into any weekly status update meeting where the topic is chip design verification, especially if formal verification is on the agenda, and it’s clear the verification department is moving much like traditional corporate environments. That is, there are generalists with loads of knowledge about many different verification tools and techniques and then there are specialists or experts who ... » read more

What’s Next For UVM?
By Brian Bailey - 28 Jul, 2016 - Comments: 0

The infrastructure for much of the chip verification being done today is looking dated and limited in scope. Design has migrated to new methodologies, standards and tools that are being introduced to deal with heterogeneous integration, more customization, and increased complexity. Verification methodologies started appearing soon after the release of SystemVerilog. Initially they were inten... » read more

Going Open Source
By Dave Kelf - 26 May, 2016 - Comments: 2

Open Source often is thought of as an alternative to commercial software licensed using fairly typical business models. For example, variants of open source Linux supplied by companies such as Red Hat charge a subscription for support and maintenance. Maybe there is an opportunity to leverage Open Source alongside commercial EDA software to provide use model advantages and open development f... » read more

ESL Flow is Dead
By Brian Bailey - 28 Apr, 2016 - Comments: 3

It was 20 years ago that Gary Smith coined the term [getkc id="48" comment="Electronic System Level"] (ESL). He foresaw the next logical migration in abstraction up from the [getkc id="49" comment="Register Transfer Level"] (RTL) to something that would be capable of describing and building complex electronic systems. He also saw that the future of EDA depended upon who would control that marke... » read more

Verification Facing Unique Inflection Point
By Brian Bailey - 10 Mar, 2016 - Comments: 0

The Design and Verification Conference and Exhibition (DVCon) attracted more than 1,100 people to San Jose last week, just slightly less than last year. While a lot of focus, and most of the glory, goes to design within semiconductor companies, it is verification where most of the advancements are happening and thus the bigger focus for DVCon. The rate of change in verification and the producti... » read more

Powerful New Standard
By Brian Bailey - 02 Mar, 2016 - Comments: 1

In December 2015, the IEEE released the latest version of the 1801 specification, titled the IEEE standard for design and verification of low-power integrated circuits, but most people know it as UPF or the Unified Power Format. The standard provides a way to specify the power intent associated with a design. With it, a designer can define the various power states of the design and the contexts... » read more

A History of (Premature) Optimization
By Neil Johnson - 22 Dec, 2015 - Comments: 0

I saw some material shared from DVCon Europe last month that suggested a competition brewing between shift left and agile in semiconductor development. As someone who’s been following shift left writing and been advocating for agile development, this kind of comparison is more than a little odd to see. It’s a comparison between two as yet amorphous development strategies, neither of which i... » read more

One Flow To Rule Them All
By Brian Bailey - 12 Nov, 2015 - Comments: 0

The new mantra of shift left within EDA is nothing new and first made an appearance more than a decade ago. At that time there was a very large divide between logic synthesis and place and route. As wire delays became more important, timing closure became increasingly difficult with a logic synthesis flow that did not take that into account. The tools subsequently became tied much closer togeth... » read more

Abstraction: Necessary But Evil
By Brian Bailey - 14 Oct, 2015 - Comments: 1

Abstraction allows aspects of a design to be described in an executable form much earlier in the flow. But some abstractions are breaking down, and an increasing amount of lower-level information has to be brought upstream in order to provide estimates that are close enough to reality so informed decisions can be made. The value of abstractions in design cannot be overstated. High levels of ... » read more

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