Optimizing Physical IP For Applications And Processors


What will the next challenges be for chip designers as the industry moves toward 28nm high-k metal gate manufacturing technology? One thing is for sure, power management may get even more painful without new innovations to handle the characteristics of 28nm. Optimization is definitely the approach that keeps creeping up as I talk with folks in the industry with ARM specifically mentioning ap... » read more

Experts At The Table: Low-Power Management And Verification


By Ed Sperling Low-Power Engineering moderated a panel featuring Bhanu Kapoor, president of Mimasic; John Goodenough, director of design technology at ARM; and Prapanna Tiwari, corporate applications engineer at Synopsys. What follows are excerpts of their presentations, as well as the question-and-answer exchange that followed. Prapanna Tiwari: Traditional techniques like clock-gating an... » read more

Experts At The Table: Low-Power Management And Verification


By Ed Sperling Low-Power Engineering moderated a panel featuring Bhanu Kapoor, president of Mimasic; John Goodenough, director of design technology at ARM; and Prapanna Tiwari, CAE manager at Synopsys. What follows are excerpts of their presentations, as well as the question-and-answer exchange that followed. Bhanu Kapoor: There are two types of power you need to consider: Dynamic power, ... » read more

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