Designing Heterogeneous AI Acceleration SoCs


A new technical paper titled "Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience" was published by researchers at University of Bologna. Abstract "Since 2013, the PULP (Parallel Ultra-Low Power) Platform project has been one of the most active and successful initiatives in designing research IPs and releasing them as open-source. Its portfolio now ranges from processor co... » read more

A RISC-V On-Chip Parallel Power Controller for HPC (ETH Zurich, U. of Bologna)


A new technical paper titled "ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation" was published (preprint) by researchers at ETH Zurich and University of Bologna. Abstract (partial) "High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems demanding complex an... » read more

Low Power HW Accelerator for FP16 Matrix Multiplications For Tight Integration Within RISC-V Cores


This new technical paper titled "RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs" was published by researchers at University of Bologna and ETH Zurich. According to their abstract: "One of the key stumbling stones is the need for parallel floating-point operations, which are considered unaffordable on sub-100 mW extre... » read more