A RISC-V On-Chip Parallel Power Controller for HPC (ETH Zurich, U. of Bologna)

By Technical Paper Link - 26 Feb, 2023 - Comments: 0

A new technical paper titled "ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation" was published (preprint) by researchers at ETH Zurich and University of Bologna. Abstract (partial) "High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems demanding complex an... » read more

Low Power HW Accelerator for FP16 Matrix Multiplications For Tight Integration Within RISC-V Cores

By Technical Paper Link - 03 Aug, 2022 - Comments: 0

This new technical paper titled "RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs" was published by researchers at University of Bologna and ETH Zurich. According to their abstract: "One of the key stumbling stones is the need for parallel floating-point operations, which are considered unaffordable on sub-100 mW extre... » read more

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A RISC-V On-Chip Parallel Power Controller for HPC (ETH Zurich, U. of Bologna)

Low Power HW Accelerator for FP16 Matrix Multiplications For Tight Integration Within RISC-V Cores

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tag: PULP

A RISC-V On-Chip Parallel Power Controller for HPC (ETH Zurich, U. of Bologna)

Low Power HW Accelerator for FP16 Matrix Multiplications For Tight Integration Within RISC-V Cores

Trending Articles

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Chiplets Make Progress Using Interconnects As Glue

Knowledge Centers Entities, people and technologies explored

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AI’s Role In Chip Design Widens, Drawing In New Startups

Key Technologies To Extend EUV To 14 Angstroms

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