Week In Review: Semiconductor Manufacturing, Test

By Karen Heyman - 06 Jan, 2023 - Comments: 0

TSMC is in advanced talks with key suppliers about setting up its first potential European plant in Dresden, Germany, according to Nikkei Asia. The company held a 3nm volume production and capacity expansion ceremony at its Fab 18. TSMC also is building 3nm capacity at its Arizona site, as well as opening a global R&D Center in the Hsinchu Science Park in the second quarter of 2023, to be ... » read more

Week In Review: Manufacturing, Test

By Karen Heyman - 19 Aug, 2022 - Comments: 0

The U.S. Commerce Department issued export controls on key technologies, including gallium oxide (Ga2O3) and diamond substrates, which are used at high voltages and temperatures, as well as EDA tools specifically developed for GAA FETs. It's not clear how this will impact EDA companies, because many of the tools that will be used for designing for GAA FETs already are in use today for finFETs. ... » read more

Week In Review, Manufacturing, Test

By Karen Heyman - 05 Aug, 2022 - Comments: 1

Post-CHIPS Act Micron is discussing a potential new fab that could employ thousands of workers, following the passage of the Chips and Science Act. Idaho is hoping it will be built near its headquarters facilities in Boise, but Micron hasn’t committed publicly. Rob Beard, senior vice president, general counsel and corporate secretary at Micron, told the Idaho Statesman the company is consi... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: semiconductor week in review

Week In Review: Semiconductor Manufacturing, Test

Week In Review: Manufacturing, Test

Week In Review, Manufacturing, Test