Week in Review – IoT, Security, Autos

By Jeff Dorsch - 04 Oct, 2019 - Comments: 0

Products/Services Cadence Design Systems is working with Adesto Technologies to grow the Expanded Serial Peripheral Interface (xSPI) communication protocol ecosystem, for use in Internet of Things devices. The Cadence Memory Model for xSPI allows customers to ensure optimal use of the octal NOR flash with the host processor in an xSPI system, including support for Adesto’s EcoXiP octal xSPI ... » read more

July’19 Startup Funding

By Jeff Dorsch - 07 Aug, 2019 - Comments: 0

During the month of July, 21 technology startups took in mega-rounds of $100 million or more. Those companies together received more than $7.5 billion. On the other end of the financing spectrum, dozens of startups got seed funding or a Series A round. The dollar amounts were much smaller. Still, they are the beating heart of entrepreneurship around the world. It also was a month when som... » read more

April’19 Startup Funding: Corporate Gushers

By Jeff Dorsch - 02 May, 2019 - Comments: 0

It was another rich month for startups, large and small. In April’s top 11 funding rounds, five were investments by big corporations or corporate venture capital funds—an investor consortium led by the SoftBank Vision Fund, PayPal, Ford Motor, NTT DoCoMo, and HAPSMobile, a joint venture of SoftBank Group and AeroVironment. Those 11 investments totaled $3.74 billion. Intel Capital was als... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: Siemens Next47

Week in Review – IoT, Security, Autos

July’19 Startup Funding

April’19 Startup Funding: Corporate Gushers