Signal Connectivity Checks Are Not Just For Design-For-Test Teams

By Pawini Mahajan and Raja Koneru The complexity with system-on-chip (SoC) design continues to grow, creating greater complexity of the corresponding design-for-test (DFT) logic required for manufacturing tests. Design teams are challenged not only by high gate counts and the array of internally developed and third-party IP integrated into their designs: the need to achieve high-quality manu... » read more