Security Improving For Low-Cost Hardware

By Adam Kovac - 05 Sep, 2024 - Comments: 0

Security has been a priority in software for decades, but only recently has it begun catching up in chips — particularly those in inexpensive devices. The disconnect is that while these devices are low-cost, they often are connected to the same networks as more sophisticated devices and repositories for valuable data. It's not unusual for the entry point in ransomware or distributed denial... » read more

Hardware Security Set To Grow Quickly

By Adam Kovac - 22 Aug, 2024 - Comments: 0

Experts At The Table: The hardware security ecosystem is young and relatively small but could see a major boom in the coming years. As companies begin to acknowledge how vulnerable their hardware is, industry standards are being set, but must leave room for engineers to experiment. As part of an effort to determine the best way forward, Semiconductor Engineering sat down with a panel of experts... » read more

Defining Chip Threat Models To Identify Security Risks

By Adam Kovac - 01 Aug, 2024 - Comments: 0

Experts At The Table: As hardware weaknesses have become a major target for attackers, the race to find new ways to strengthen chip security has begun to heat up. But one-size does not fit all solution. To figure out what measures need to be taken, a proper threat model must be assessed. Semiconductor Engineering sat down with a panel of experts at the Design Automation Conference in San Franci... » read more

Architecting Hardware Protection For Data At Rest, In Motion, And In Use

By Bart Stevens - 05 Jan, 2023 - Comments: 0

Planning the security architecture for any device begins with the security threat model. The threat model describes the types of attacks that the device or application may face and needs to be protected against. It is based on what attackers can do, what level of control they have over the product (i.e., remote, or direct access), and how much money and effort they are willing and able to spend... » read more

Advancing The Maturity Of Your Hardware Security Program

By Cycuity (Formerly Tortuga Logic) - 06 Jul, 2022 - Comments: 0

Where are you today on the Hardware Security Maturity Model? Hardware security is a journey. LEVEL 1: Foundational Define security requirements and validate hardware security features are working with functional verification. LEVEL 2: Basic Introduce threat models and security verification requirements while also enabling hardware protection mechanisms. Ad hoc security verification beg... » read more

Security Starts With A Threat Assessment

By Bart Stevens - 06 Jan, 2022 - Comments: 0

Developing the security architecture for an electronic device begins with building a threat model wherein we ask these questions: What is the operational environment in which the device needs to function? What type of attacks can be identified? What level of access does a potential attacker have to the device? What possible attack paths can an attacker exploit? What resources (... » read more

Architecting Hardware Protection For Data At Rest And In Motion

By Bart Stevens - 02 Dec, 2021 - Comments: 0

Planning the security architecture for any device begins with the threat model. The threat model describes the types of attacks that the device or application may face and needs to be protected against. It is based on what attackers can do, what level of control they have over the product (i.e., remote or direct access), and how much effort and money they are willing and able to spend on an att... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer