RISC-V Pros And Cons

By Ann Mutschler - 29 May, 2017 - Comments: 7

Simpler, faster, lower-power hardware with a free, open, simple instruction set architecture? While it sounds too good to be true, efforts are underway to do just that with RISC-V, the instruction-set architecture (ISA) developed by UC Berkeley engineers and now administered by a foundation. It has been known for some time that with [getkc id="74" comment="Moore's Law"] not offering the same... » read more

Toward Continuous HW-SW Integration

By Ann Mutschler - 25 May, 2017 - Comments: 0

Hardware is only as good as the software that runs on it, and as system complexity grows that software is lagging behind. The way to close that gap is to improve the [getkc id="100" kc_name="methodology"] for developing that software in the first place. That includes making sure updates are verified and tested before being pushed out to devices, adding the same kinds of detailed checks that ... » read more

The Week In Review: Design

By Jesse Allen - 02 Dec, 2016 - Comments: 0

Deals Kilopass extended its deal with ICScape, which makes a Parallel SPICE simulator, for eNVM IP at advanced finFET nodes. Kilopass has been working with ICScape for the past couple of years as part of its qualification methodology. IP Silvaco released three MIPI I3C sensor controller IP cores. Developed with NXP to push adoption of I3C, the new products are an Advanced Slave core wi... » read more

The Week In Review: Design/IoT

By Jesse Allen - 30 Oct, 2015 - Comments: 0

Tools Aldec introduced Hybrid Emulation including support for ARM Fast Models. Aldec says the capability to link an SoC emulation hardware platform with a virtual platform allows both software and hardware teams to work on the most up-to-date version of the project, long before first silicon is available, or even much of the RTL or IP has been completed. eSilicon's online quoting tools fo... » read more

What Will Change In Design For 2015?

By Brian Bailey - 15 Jan, 2015 - Comments: 0

This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already res... » read more

New Winners And Losers

By Brian Bailey - 24 Jul, 2014 - Comments: 0

During DAC 2013, Robert Colwell of DARPA said he was attempting to prepare the U.S. Dept. of Defense for what he believes is the cataclysm caused by the end of [getkc id="74" comment="Moore's Law"]. He asked the question, “What happens when we don’t have a new technology that doubles the number of transistors every couple of years?” Colwell believes that power is the primary reason why... » read more

Moore’s Law Tail No Longer Wagging The Dog

By Brian Bailey - 26 Jun, 2014 - Comments: 3

In a recent special report titled “Will 7nm and 5nm really happen?” Semiconductor Engineering outlined the progress being made for new production nodes and the progress being made to overcome the technological challenges that they contain. But who are the likely candidates for those new nodes and who is going to pay for their development, including the EDA tools that will be necessary to ut... » read more

Without Moore’s Law: EDA

By Brian Bailey - 26 Jun, 2014 - Comments: 3

Semiconductor Engineering is examining the assertion about the end of Moore’s Law in a number of different ways. The special report, “Will 7nm and 5nm really happen?” looked at the technical aspects related to continuing into finer geometries. “Moore’s Law Tail No Longer Wagging the Dog” asked the question about the economics of people being able to afford to go to the latest node. ... » read more

Big Memory Shift Ahead

By Brian Bailey - 22 May, 2014 - Comments: 1

System architecture has been driven by the performance of [getkc id="22" kc_name="memory"]. Processor designers would have liked all of the memory be fast [getkc id="92" kc_name="SRAM"], placed on-chip for maximum performance, but that was not an option. Memory had to be fabricated as separate chips and connected via a Printed Circuit Board (PCB). That limited the number of available I/O ports ... » read more

Powerful Memories

By Brian Bailey - 07 May, 2014 - Comments: 1

Memory consumes more of the surface area of a die than any other component. So what changes have happened over the past few years to reduce the power consumption of memories, and where are the big opportunities for saving power? Let's take a closer look. A Growing Concern One of the key drivers for SoCs is the desire to reduce product costs, reduce form factors, reduce power, increase perfo... » read more

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