Hybrid Simulation Picks Up Steam

By Ann Mutschler - 26 Jan, 2017 - Comments: 0

As electronic products shift from hardware-centric to software-directed, design teams are relying increasingly on a simulation approach that includes multiple engines—and different ways to use those engines—to encompass as much of the system as possible. How engineers go about using these approaches, and even how they define them, varies greatly from one company to the next. Sometimes it... » read more

Formal’s Roadmap

By Brian Bailey - 12 Dec, 2016 - Comments: 0

Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

Formal’s Roadmap

By Brian Bailey - 30 Nov, 2016 - Comments: 0

Gaps In The Verification Flow

By Brian Bailey - 01 Nov, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at [getentity id="22017" e_name="Mentor Graphics"]; [getperson id="11079" comment="Anupam Bakshi"], CEO of [getentity id="22168" e_name="Agnisys"]; [getperson id="11124" comment="Mike Bartley"], CEO of [getentity id="22868" e_name="Test and Verification... » read more

Too Big To Simulate?

By Ann Mutschler - 27 Oct, 2016 - Comments: 2

With system design complexity set on a steady upward trajectory, there are situations in which traditional simulation just can’t keep up. The alternative—and one being used by Google, Uber, Ford, GM, Volvo, Audi and others with autonomous vehicles— is to test cars on the road and collect data for later analysis. “They're not simulating, they're just doing it all in the real world ... » read more

Emulation’s Footprint Grows

By Brian Bailey - 27 Oct, 2016 - Comments: 0

It wasn't that many years ago that [getkc id="30" comment="emulation"] was an expensive tool available to only a few, but it has since become indispensable for a growing number of companies. One obvious reason is the growing size of designs and the inability of [getkc id="11" kc_name="simulation"] to keep up. But emulation also has been going through a number of transformations that have made i... » read more

Gaps In The Verification Flow

By Brian Bailey - 29 Sep, 2016 - Comments: 0

The Future of UVM

By Neil Johnson - 26 Aug, 2016 - Comments: 7

It’s time for a frank discussion on the future of [gettech id="31055" comment="UVM"]. Given how UVM usage has grown and the number of teams that rely on it, I think this conversation has been a long time coming. Is continuing to use UVM the right thing to do? Do we have hard evidence that supports our continued usage of UVM? Do we actually benefit from it or do we just think we benefit? ... » read more

Optimizing Testbench Acceleration Performance

By Mentor, a Siemens Business - 10 Aug, 2016 - Comments: 0

Part 3 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three papers, architectural and modeling requirements are described, followed by a recommended systematic approach for maximizing overall testbench acceleration speed-up and achieving your ultimate performan... » read more

Making Verification Easier

By Ann Mutschler - 28 Jul, 2016 - Comments: 0

SoC design teams increasingly are confronting complexity in the quest to target application segments, but at the same time they are struggling to more quickly reduce risk in their designs while also speed up testing to make sure everything works. Those often-conflicting goals have transformed [getkc id="10" kc_name="verification"] IP from an interesting concept to a must-have tool for advanc... » read more

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tag: UVM

Hybrid Simulation Picks Up Steam

Formal’s Roadmap

Formal’s Roadmap

Gaps In The Verification Flow

Too Big To Simulate?

Emulation’s Footprint Grows

Gaps In The Verification Flow

The Future of UVM

Optimizing Testbench Acceleration Performance

Making Verification Easier