Security Concerns Weigh Down Open-Source EDA


Open-source EDA tools are free, readily available, and growing in numbers, but many chipmakers are wary of using them due to security concerns. On the plus side, proponents say these tools can help attract fresh new talent to chip design. Yet despite their spread online — GitHub alone has more than 140 EDA-specific repositories — using visible source code can provide new avenues of attac... » read more

New Methodologies Create New Opportunities


Experts at the Table: Semiconductor Engineering sat down to discuss what open source verification means today and what it should evolve into, with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Ashish Darbari, CEO of Axiomise; Simon Davidmann, CEO of Imperas Software; Serge Leef, program manager in the Microsystems Technology Office at DARPA; Tao Liu, staff hardwa... » read more

Simplifying And Speeding Up Verification


Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; Nasr Ullah, senior director of performance architecture at SiFive. What follows are excerpt... » read more

Week In Review: Design, Low Power


Synopsys completed its acquisition of QTronic GmbH, a provider of simulation, test tools, and services for automotive software and systems development. Terms of the deal were not disclosed. Synopsys launched the PrimeECO design closure solution, a signoff-driven solution that the company says achieves signoff closure with zero iterations. The tool includes a machine-learning-driven Hybrid Ti... » read more