The Week In Review: Design/IoT

By Jesse Allen - 13 Nov, 2015 - Comments: 0

Predictions Wally Rhines, Mentor Graphics' chairman and CEO, was presented with the Kaufman Award last night for outstanding achievement in electronic design. In his acceptance speech, he plotted the growth of the EDA industry at a consistent 2% of the semiconductor industry for the past couple decades. But he noted that with a shift to system design automation, that number would rise from t... » read more

The Week In Review: Design/IoT

By Jesse Allen - 06 Nov, 2015 - Comments: 0

Mentor Graphics began selling infrastructure hardware this week, including an end-to-end IoT solution that includes a reference design for a customizable gateway, a cloud backend, and runtime solutions on which to build a wide array of IoT edge devices. Mentor also released virtual platforms for Altera's Arria 10 SoC FPGA, and updated its Valor PCB manufacturing process to focus on Industry 4.0... » read more

The Week In Review: Design/IoT

By Jesse Allen - 16 Oct, 2015 - Comments: 0

M&A Continuing to seek economies of scale in the IP industry, VeriSilicon and Vivante are combining forces. "This transaction creates an extensive semiconductor IP portfolio that will now include GPU cores, vision image processors, digital signal processors, video codecs, mixed signal IP and foundry foundation IP," said Wayne Dai, VeriSilicon chairman, president and CEO. The merged compa... » read more

Making Waves In Low-Power Design

By Barry Pangrle - 16 Jan, 2014 - Comments: 0

Barry Pangrle In a blog last April we looked at a potential candidate technology that just might be able to produce an economically feasible method for implementing delay insensitive circuits in CMOS. The basic idea behind this technology has been around since at least the 1990s and is better known as Null Convention Logic™ (NCL). Much of the work in this area was pioneered by Karl Fant and ... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Wave Semiconductor

The Week In Review: Design/IoT

The Week In Review: Design/IoT

The Week In Review: Design/IoT

Making Waves In Low-Power Design