Taking Steps Toward Hybrid Memory

Intelligently utilizing multiple types of memory in a single subsystem.


What is the memory subsystem of the future, and how do we get there? Since our Hybrid Memory research program began, Rambus Labs and its industry partners and collaborators have made significant progress under the banner of OpenPOWER and OpenCAPI Foundations, an open development community based on the POWER microprocessor (mP) architecture. Rambus Labs is using the Wistron POWER9 systems’ OpenCAPI interfaces to create the hybrid memory development prototype.

This research project involves multiple memory types. It involves not just predetermined algorithms, like those of today. It uses the idea of the software learning its own access patterns and then feeding those learnings to the hardware to make increasingly better decisions about how to use these many different memory types in the system.

This new memory subsystem falls into the category of hybrid memory. We define it as a memory subsystem composed of more than one type of memory, with different attributes, like different latency, power, and bandwidth, for instance.

The hybrid memory subsystem, itself, takes care of all the management, such that user software never knows that it’s happening. By this definition, we already have a slightly hybridized memory subsystem in today’s computers because SRAM and DRAM are in the same memory subsystem. We have SRAM caches and DRAM main memory. And user software doesn’t really know that the cache is there other than it sees lower latency compared to an all DRAM subsystem.

We can simulate the vision of what the ultimate hybrid memory subsystem looks like, but at some point, we have to buckle down and build one to ensure that our vision can be implemented.

Rambus Labs has done the first step and simulated. Now, we’re doing the next step and building it in actual hardware. It’s designed to accommodate present and future needs for exploration of hybrid memory subsystems and serial attached memory. The other point to make is it uses a Xilinx XCVU9P with bigger devices possible. We’ve created the necessary interface blocks inside that FPGA to allow others to implement their vision and compare.

We’re currently collaborating with memory vendors to get their emerging memories working on this card. We are also collaborating with universities and other industry partners allowing them to implement their management schemes on this card to see how they perform.

Here at Rambus Labs, we emphasize the importance of searching out more collaborators to sustain this research in an open fashion as there will never be enough time to explore all possible ways of hybridizing memory. We’ve developed some excellent methods of hybridizing certain types of memory. We believe this platform can enable the industry as whole to leverage the data to judge various ways of hybridizing different types of memory, opening a future with multiple memory types in server memory subsystems.

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