The Case Against 8051

Why this older MCU is impractical for IoT applications.

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With the rise of Internet of things, sensors controlled by embedded processors are being installed in homes, offices, factories, and metropolitan infrastructure, power grids, and just about everything else. Because these intelligent IoT devices are deployed in large quantities everywhere, their cost must be very low compared with the mobile devices everyone carries with them every day. Besides sensors, these IoT devices contain analog-to-digital converters to transform the sensor data for the embedded processor to manipulate and a communications link to route the processor’s output to remote data centers via the Internet.

The main design requirements on an IoT device are cost, performance/power, and security to prevent hackers from taking control of the device. To keep costs low, the 8051 seems the obvious choice as the embedded processor in this new breed of smart device. However, the 30-year old 8051 may come with hidden costs and disadvantages that make it less desirable than newer 32-bit CPU cores designed within the last decade with features tailored to this emerging new application. This article advances the argument for 32-bit CPU cores against the 8051 presenting evidence that supports the claim. http://www.embedded.com/electronics-blogs/cole-bin/4426602/The-8051-MCU–ARM-s-nemesis-on-the-Internet-of-Things-

First is the requirement of cost, which must be measured not only in die area of the embedded processor and its peripherals, but also in the amount of memory needed to hold the program for the CPU. While the die area consumed by an 8051 might be small, the amount of code needed for its program is on the order of five to six times more than for a 32-bit core. An 8051 will require on the order of five times the code size of a 32-bit processor core.

This false cost economy can best be demonstrated by examining the requirement for performance. Consider the task of adding two 16-bit numbers and dividing by two. An 8051 requires 12 bytes of code and 11 CPU cycles to perform this task. Performing the same task on a 32-bit CPU requires only 4 bytes and two cycles. The first cycle adds the two numbers and the second performs the divide operation by a 1-digit shift. The performance gap increases with a more complex operation such as a 16-bit multiply, which requires 48 bytes of code to perform the multiply and 48 cycles to achieve a result. The 32-bit processor achieves the result in a single cycle. Another common function required in typical computer operation is the memory copy. For example, to copy five consecutive 32-bit memory contents to general-purpose registers or the other way around, the 8051 requires 20 bytes of code and 20 cycles to perform the task. In comparison, the Andes N801 CPU takes 8 bytes and 7 cycles.

In summary, 8051 arithmetic operations require four times the code size of a 32-bit processor and 16 times the number of compute cycles of a 32-bit processor. This performance is apparent in the large difference in the Dhrystone (DMIPS/MHz) benchmark between the 8051 and a 32-bit processor. The former produces 8.5 DMIPS when running at 100 MHz. The latter achieves 151 DMIPS at a 100 MHz clock rate, a 20 times difference.

However, one benefit of the 8051 is that it comes with peripherals including interrupt controller, timer, GPIO, and UART, etc. For the typical 32-bit microprocessor, these are added elements. However, even with peripherals integrated with the 8051, the gate count of a microprocessor plus peripherals is not more than a fully equipped 8051.

Besides cost, the other concern in an IoT device is power. Power savings features not available on the older 8051 CPUs are common in many modern 32-bit cores. The Andes N801, for example, comes with a power savings mode but also offers additional capability, including a technique that allows the CPU clock rate to be dynamically throttled. The CPU can be running at full 100% with a high processing load and then scale down to 10% when the load is lessened. In addition to the CPU, there are power savings incorporated into the peripherals surround the CPU, something not incorporated in the earlier 8-bit processors.

In addition, 32-bit processors come with improved architectural features that make them far superior to 8-bit alternatives. An 8051 would fetch the program an instruction at a time from flash. A feature on the Andes N801 called FlashFetch can be used to reduce power or boost performance. It holds a small number of instructions to eliminate the need to access them from flash, a power consuming operation. Because the AE210P is a new architecture, these features are not commonly available on older 32-bit CPUs designed over 30 years ago.

The third requirement of an IoT device is security. For the IoT device, security requires blocking attacks of the software/firmware of the device by hacking the JTAG interface or the program/data bus of the device. It also requires blocking attacks that come from monitoring the power profile of the device using differential power analysis. Fixing the JTAG vulnerability is a matter of not making the JTAG port available on the I/O pins of the device, or if the JTAG port is needed for further debugging, securing the port with a key. For the program memory, a logic analyzer probe can easily detect the contents of memory.

Using a secure 32-bit CPU core, a secure JTAG interface can require the user to pass a certification process that requires a pass code stored inside the chip containing the embedded core or from an external server before gaining access. To thwart attacks on the program/data bus of the device, the secure CPU scrambles the information being transferred between external memory and the CPU to make it unintelligible to the hacker.

Finally, a differential power analysis hack is commonly used to detect encryption keys stored within an embedded CPU. Differential power analysis relies on large numbers of repetitive operations. By analyzing the power profile of these repetitive calculations, hackers can extract the key information stored within the chip. The solution is to inject random patterns into the profile of the CPU, thus making power analysis far more difficult.

In conclusion, considering the IoT requirements of cost, performance/power, and security, the 8051 fails to measure up to the latest generation of 32-bit CPU architecture. The older technology 8051 requires more die area, draws more power while lacking the compute power, and is vulnerable to hacking attacks commonplace today.


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  • iZombie

    some good points, except with the crypto – the algorithms need to change radically and not be blessed by some gummit entity. even with random noise introduced during computation, an algorithm like AES is designed to be breakable. look at the open source project “ChipWhisperer” and the plethora of DEFCON and CCC videos on cracking AES. it is security theater, and until that changes, vendor and engineer beware…

    also with JTAG – who watches the watchers and ensures no backdoors are making it to the die mask? most of the silicon is spun in countries that don’t have other countries best interests at heart.