The Challenges Of Designing 28G And 56G SerDes IP

The industry move to 56 Gbps PAM4 is undoubtedly one of the greatest challenges currently facing SerDes IP designers and their customers. To begin with, shifting to 56 Gbps PAM4 immediately causes a loss of 9 dB. While the baud rate is 28 Gbaud, there are now three eyes stacked on top of each other. Nevertheless, there is still demand for 35+ dB reach. This is a significant challenge which requires adopting an ADC based architecture for next-generation SerDes IP.

Of course, even 28 Gbps NRZ signaling poses significant challenges for customers integrating SerDes IP. Firstly, the PCB material requires an upgrade. Secondly, careful analysis needs to be performed on the package and PCB to ensure there is adequate isolation to minimize crosstalk.

This is precisely why it is critical for IP vendors to offer IBIS AMI simulation models, which allows customers to understand the results of their specific package and board design choices. The s-parameter models are typically made available by cable and connector vendors. The s-parameters for the package and PCB can be extracted or measured with a VNA. In addition to IBIS AMI simulation models, piecewise linear current models (PWL) are needed for simulation of the analog power rails.

Beyond simulations, SerDes IP should provide highly programmable circuits and contain debug interfaces to easily gather important analog and digital information, i.e., an ATEST pin that allows measuring various analog voltages and currents. These are important capabilities that allow the IP to be debugged during bring up and adjust the performance itself if necessary. Moreover, on-chip eye monitors are useful to show how well the equalizer has opened the eye, along with extensive scripts to help sweep parameters during the final ASIC characterization.

Perhaps one of the most important aspects of SerDes IP design is the test-chip process. To be sure, there isn’t a true substitute for taping out a test chip, verifying it in the lab and enabling first–time-right silicon. This is one of the reasons it is so important for SerDes IP blocks to be architected with a high level of integrated programmability. Avoiding a ‘dead’ first-time chip is critical, as the silicon must be equipped with initial functionality to ensure the verification flow remains on track. SerDes IP vendors do not have unlimited cycles to model and analyze all possibilities and configurations. As such, experience and good judgement are both needed to decide when to pull the trigger on the test chip with good certainty of a quality result.

Last, but certainly not least, it is critical for vendors to accommodate a wide variety of SerDes customer design requests. This can be accomplished by pulling in a range of experts at different stages of the design, such as package and PCB design experts and layout gurus, as well as signal integrity and power integrity specialists. Put simply, the SerDes IP design process must be collaborative as customers cannot be left on their own to ensure the successful completion of a 28 Gbps ASIC.