The LP R&D Ecosystem

Chip design innovations happen by a variety of means.

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I don’t know about you, but I’m always fascinated to learn new things about chip design. New techniques for power reduction, new ways to use existing tools, new tools in general. Some of this is happening at universities, some in happening in industry consortiums or partnerships, and despite what some people say from time to time, there is still innovation happening within the EDA companies.

The ‘EDA way’ of innovating for the large players at least has been to acquire smaller players or startups, but in the two decades of following this industry, I regularly hear about new tools or techniques developed from scratch within the R&D organizations of Cadence, Mentor Graphics and Synopsys. If I’m wrong on one of those, someone please correct me.

On the university side, there is work happening constantly, even if they only talk about a fraction of it. We cover as much of it as possible in our Power/Performance Bits, Manufacturing Bits and Systems Bits columns. How quickly some of that technology makes it to a commercial point is definitely something that would be interesting to dive into. It seems safe to argue that the EDA industry might not exist today had it not been for various technologies developed within an academic research environment that were transferred and/or licensed to commercial tool providers.

In any case, the interplay within this entire ecosystem is where the magic happens, and ultimately has enabled a tremendous amount of innovation that engineers employ in their designs every day.

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