The Network Is The SoC…

By Frank Ferro
SoC design continues to challenge semiconductor and system companies in their pursuit to create a better user experience for a wide range of products. Given this, I was pleasantly surprised to see that two of the “Ten technologies that will change the world in 2013,” according to EETimes (December 2012 issue) were SoC-related.

One is virtual SoC prototypes and the other is IP subsystems. These technologies are right up there in the top 10 list with heterogeneous networks, gesture recognition and 3D printing (which by the way I struggle to ‘wrap my head around’ because this is a real Star Trek replicator!) Both virtual SoC prototypes and IP subsystems are making such lists because they are now necessary pieces in the SoC design puzzle. The complexity of SoCs designed in 28nm process technology and below are becoming too unwieldy for design teams to manage as more and more functionality is being crammed onto the die. Note that that 3D FinFET transistors also made the top 10 list (14nm and below).

Having the ability to create virtual prototypes addresses not only SoC complexity, but also the time-to-market pressure, by pipelining software development in advance of silicon. Virtual prototypes can be a cost effective alternative to FPGA emulators for hardware and software development. However, they also can be used in conjunction with FPGAs for hardware testing and third-party IP integration. Clearly defining the architecture based on a more detailed understanding of the system’s performance behavior, in advance of the SoC implementation, will save time and cost during the implementation phase, ensuring the SoC meets design specifications.

Along with virtual prototypes, IP subsystems are clawing their way out of an esoteric world as they emerge as a key component in a complex SoC design strategy. IP subsystems are a way to ‘divide and conquer,’ where advanced functions such as graphics, audio or video are addressed by the subsystem. The advantage of this approach is that these functions can be tested and verified at the unit level, then integrated with the top-level SoC functions. Another advantage is that subsystems are available as commercial IP blocks from multiple vendors, making for good competition. Plus, the expertise for these functions does not need to exclusively reside ‘in house.’ Semico Research predicts 25% of the SoCs that ship next year will include subsystems, with this number increasing to more than 65% in 2015.

SoC Design is Fabric Design: As collections of subsystems begin to make up a larger percentage of the SoC, integrating these subsystem along with other IP components is the real challenge. A customer recently noted that the speed and success of an SoC program is tightly coupled to their ability to do the fabric design (or the on-chip communications network). Being a supplier of on-chip networks, it is certainly encouraging to hear customers elevate the importance of this IP in their SoC methodology, equating it with the success or failure of a program. Fortunately (or unfortunately), this is true because the network touches every aspect of the SoC design from early architecture exploration all the way through to back-end layout. So the on-chip network is not only a critical IP block connecting all the cores in the system, it is also is a tool for architecture exploration and performance analysis. And finally, it is a platform methodology to allow the rapid and repeatable assembly of the SoC, enabling design teams to meet the rapidly changing market requirements.

PPA: Understanding tradeoffs around performance, power and area (PPA) are essential to ensure that architectural intent can be realized in silicon. Connecting so many cores and subsystems together creates natural contention points in the network which, if not managed, will mean poor performance for the various usage scenarios or failure of the SoC completely. To answer these PPA questions, RTL or SystemC models of the on-chip network allow the SoC architect and designer to model and analyze critical data paths in order to optimize the system (e.g. optimize buffer sizes and minimize wires). Architectural features in the network, such as virtual channels, QoS, and true non-blocking flow control (not simply request and response pipelining), provide the concurrency necessary to keep the performance up and the gate-count down. Features such as virtual channels also help with the back-end layout implementation because the logical network design is separated from the physical layout, thus avoiding performance problems late in the design as components are shifted on the die.

Mainstream: SoCs are now the critical component for leading-edge products in all the major market segments (consumer, communication, networking, enterprise, automotive). Successful SoC execution therefore is key to the success of both system and semiconductor companies, and hence the visibility. A better SoC methodology built around the on-chip network fabric is necessary to improve IP integration, help meet performance goals, and to avoid back-end layout problems (timing closure). Being on a top ten list is nice as long your SoC is the top seller.

—Frank Ferro is director of product marketing at Sonics.