The Power Of IP

By Ann Steffora Mutschler
As the number of design starts goes down the corresponding complexity of SoCs has gone up—and continues to grow. Everyone is looking at the value they can bring to the table as increasing proportions of SoCs are either reused from pre-existing IP within the company designing the chip or brought in from outside.

Because is economically impractical to start an SoC design from scratch, an estimated 70% to 90% of all new designs is re-used IP. This is making engineering teams choose very carefully what to implement themselves as their own value add and what to bring in from the outside. And that’s where the power issues begin.

“One of the big issues around IP integration is verifying the IP for the purpose you are using it for in the next design, said Pete Hardee, director of solutions marketing at Cadence Design Systems. “Putting IP in a new design with a different power intent means a lot of verification needs to be done and…the IP blocks themselves can be complex enough that they have their own power intent built into them. An IP block may have multiple power domains. It may have different supply pins for the different switched power rails that it’s got internally. It may not be clear which I/O pins are isolated and which ones need isolation.” All of these issues add up to a very complex problem when you’ve got power intent built into the IP block itself.

Some IP blocks have very complex power intent. Processors commonly implement dynamic voltage and frequency scaling, which is fairly complex, while memory IP (including embedded memory and off chip memory) often implements dynamic frequency scaling and sometimes multiple voltage, with the retention level possibly using some techniques like body biasing, Hardee continued.

Another issue in multivendor IP integration is that IP traditionally tends to be black box. “The IP vendor doesn’t necessarily want to share all the details of what’s in that IP. How is the power intent information, the power scheme that’s held with that IP block, communicated? Right now we see that there is very little support for that,” he said.

John Heinlein, vice president of marketing for ARM’s Physical IP Division, agrees there is an issue with different standards being used and at different levels. “On the one hand you have to ask what the design side criteria is being used by different vendors, and what the methodology was used to characterize power and performance. Having those standards be different may mean that there are inconsistencies when you bring together IP.”

Another problem is that different corners are employed for the voltage, temperature and environments being used. It is important that these be consistent in order to compare apple to apples, he noted.

Other challenges include support for different methodologies, support for a broad EDA ecosystem, and support for different process technologies. “At the physical IP level it’s fundamentally tied to a specific process and so you need to be able to support a broad range of process technologies,” Heinlein stressed.

Internally developed or sourced IP?
Given these challenges, one does wonder whether it is easier to integrate IP that is internally-developed or IP obtained from an external source.

“With internally-developed IP typically you’d have a lot more access to the history of that IP and every situation that it’s been used in. You’d have a lot more access to the full design files for it so you’ve got a lot more visibility into it,” said Cadence’s Hardee. “For external IP you’re in the hands of the IP vendors. A lot of IP vendors do a very good job. They are delivering their IP with the power intent file and we are working with all the major IT vendors to do that. But considering the power aspect of IP is another level of complexity that means if the IP vendor hasn’t paid attention to it and hasn’t done a good job, it’s going to be much more difficult for the IP user to integrate it and have it working correctly.”

Internal IP tends to be more customized and more narrowly focused for the users in-house infrastructure, its in-house EDA flow and methodologies, which has pluses and minuses, noted Heinlein. “On the one hand for their purposes that may be desirable. But on the other hand it limits their portability to other flows, it limits their ability to work with outside customers and partners who may need a different methodology.”

Once IP is obtained, design engineers sometimes want to use it in ways other than it was designed to do. Hardee noted that when this happens a different power intent could warrant the IP being switched off at various system modes and checking to make sure the isolation between power domains is correct. “I may be using an IP at a voltage level that is different from the one it was fully verified in. If I’m doing that I need to be aware of that fact—that I’m doing it by design and not by mistake. And if I am using the IP to implement any power intent that it wasn’t originally designed for I have to do all the verification to make sure that it operates as I expect it to in the new circumstance.”

Ken Brock, director of physical IP marketing at Virage Logic, echoed the comments. “People will try to use things as they were not intended.” Typically they hear from users, “Oh, we’ve got this particular memory and we want to use it at this very high-temperature,” even if it wasn’t designed to do that.

“At very high temperatures, very low voltages is where it mostly happens because people want to save power. Memories are very sensitive to low voltages, and while we go to great extremes to be able to provide the memories that run at the lowest voltages eventually they hit the point where they forget,” Brock said.

Because memories are more sensitive to power because of their cell structure, Virage uses foundry-supplied bit cells with design rules that are tighter than the regular ones. ARM likewise works with customers to provide characterization for those kinds of unique environments.

IP Integration Impacts Voltage
When it comes to IP integration, low-voltage support is important, has always been important, is becoming even more important, and must be “baked in” at the lowest levels of design, Heinlein said. “ARM collaborates with the foundries to make sure their low-level processes support the voltage operation. We’ve been taking a leadership position with foundries to try to drive the low voltage operation in the best direction for the industry. Too, you have to put circuit innovation and design innovations in place to support low-voltage operations and we are doing this as well,” he said.

With memories specifically, “you’re going to architecture memories in a specific way to support low-voltage operation. There are a number of things you can do there. In the case of logic, one of the things that happens with voltage is that you typically have multiple voltage domains in your chip,” he continued.

To deal with this, ARM has what it calls a power management kit (PMK) that is specifically designed to address the complexity needs and the circuit needs for chips with multi-voltage islands, incorporating things like level shifters to help facilitate connections between different voltage islands. “You can think about it like a power converter: It is an interface circuit that helps bridge between different voltage domains. Likewise, power gating is an important area and is becoming pretty much a standard thing for people using advanced SOCs to save power,” Heinlein explained.

Further, while mix-and-match may work well in the fashion world, one of the things that happens when low power and non-low power IP is combined in a single design is complexity as multi-voltage domains come together.

“One of the reasons you have voltage domains is if you have perhaps some IP that wasn’t designed, for example, for power gating or wasn’t designed to be powered down. You’ll tend to find power is managed at different levels,” he continued. As such, methodologies for looking at power in more and more detail continue to evolve and grow.

Tools, Techniques Help Bridge the Gap
To account for the challenges of integrating multivendor IP, moving up in abstraction can help mitigate the issues outlined above.

“The good thing that has come out over the past couple of years is the EDA vendor low-power flows that are characterized by Synopsys pioneering UPF, and Cadence, CPF which use two slightly different approaches to solve basically the same problem,” Brock noted.

“In doing that, it describes the intent of what you’re building so that all the tools that are looking at the IP know what to do with it… this was a very necessary step,” he said.

Another way for engineers to smooth the IP integration process is to start planning as early as possible. All of the major EDA tools vendors—Synopsys, Mentor Graphics and Cadence—have solutions for modeling power at the architectural level. That modeling now has to include power awareness in software, as well.

“Once you get into the netlist, you can optimize at the transistor level, you can optimize your clock tree, and you can do multi-threshold voltage optimization and various other things,” said Hardee. But it’s really the architecture level changes that make the big difference, and that’s where we need to make sure that you get the accuracy of estimation to be able to make the right changes.”