The Real Value Of An LP Methodology

By Luke Lang
“What are some of the low-power mistakes that you have seen?” That is, by far, the most popular question asked by designers. And it’s a very good question. Why re-invent the wheel? Why repeat mistakes? It’s a lot easier to learn from someone else’s mistakes than from your own.

Clearly, every company is different, and every design is different. But there are lots of commonalities. One of the most common low-power mistakes is not following the correct low-power methodology.

I apologize for using what is probably the most over-used word in EDA – methodology. If I had a dime for every time that I have heard, read, or used that word, I might be competing with Bill Gates and Warren Buffett on the Forbes list of richest people.

So what exactly is methodology, anyway? To me it’s a proven recipe (method) that will lead to success. In a recipe we can vary the amounts of ingredients or even substitute other ingredients to suit our taste. Like recipes, a good low-power methodology must be able to accommodate various design requirements, techniques, libraries, etc. But more important, a good methodology also contains a list of guidelines that prevent us from getting into trouble.

Many designers equate guidelines with restrictions. Some designers do not like the restrictions imposed by a low-power methodology. It is important to understand why these restrictions are necessary—and that restrictions are not unique to low-power methodology.

EDA tools help us to be incredibly productive, especially in an RTL-to-GDS2 digital flow. A small team can design a multimillion-gate chip. But EDA tools are not artificial intelligence-based and do not have human intuition. They are rule-driven and crunch the numbers based on these rules. If we don’t follow the rules, the tools crunch the wrong numbers. That’s why we have all kinds of rule checkers.

Here is one simple but real example of rule-based design: A few years ago I used a heavily loaded but static test signal to gate a functional signal. I was trying to reduce area and didn’t want to buffer the test signal that only toggles in test mode. This led to a timing violation because the gating cell had a huge output slew. Then I remembered that the output slew is a function of the worst-case input slew. Even though the test signal doesn’t toggle at all, its slow input slew caused a slow output slew for the gating cell. We can say that the real circuit will not have a slow output slew. That is true, and SPICE simulation will prove that. But we don’t want to SPICE every path. So we live with this restriction and clean up all design rule violations.

That was a non-low-power restriction. For low-power methodology, one of the most fundamental restrictions is that power intent should not reference cell instance or associated pins. The reasons are equally fundamental. Standard cells may not be instantiated in RTL. They could be optimized away during synthesis or place and route. Setting ‘don’t touch’ on these cells restricts optimization.

The way to work within the low-power methodology is to add logical module wrappers around logic or macros that we need to reference. For example, we have an isolation control signal driven from the iso_cntl register. Once synthesized, this isolation control is driven from iso_cntl_reg/Q. After DFT insertion, this isolation control could be driven from an even more complex logical function. If we take this route our power intent file must be changed at each design stage to accommodate the above name/function change. But at the end how do we know that the power intent is correct and consistent at every stage? A better approach is to put the control logic inside a power control module. The isolation control is driven from an output pin of the power control module. We can change all the logic inside the power control module, but the power intent file would remain constant. This allows us to maintain a golden power intent file throughout the flow.

Adopting a low-power methodology enables us to automate many complex and time-consuming design steps. It represents a huge increase in productivity and enhances our chances of success. There is plenty of leeway to allow a fair amount of customization. But please keep in mind that this is far from full custom. Understanding and staying within the guidelines is absolutely essential.

–Luke Lang is a senior product engineering manager at Cadence.