The Week In Review: Design

PCIe 4.0 IP; analog resource; DAC attendance.


Tools & IP

Synopsys uncorked PHY and Controller IP for PCI Express 4.0 architecture, which the company says reduces latency by up to 20% and area by 15% compared to the previous implementation. The IP supports lane margining to assess performance variation tolerance.

PLDA announced a PCIe 4.0 development platform, and provides a PCIe 3.0-x8 (upstream) to PCIe 4.0-x4 (downstream) Integration Backplane

Cadence debuted, a new user-community web portal  to provide access to materials related to PSpice analog and mixed-signal simulation and analysis in one central location.


MagnaChip selected Mentor Graphics’ Analog FastSPICE Platform for circuit verification and device noise analysis of their analog and mixed-signal designs including display drivers, power management ICs, and PLLs.


This year’s DAC saw a boost in attendance from the last time it was in Austin, in 2013, with a slight increase in overall attendees and a 45% increase in technical conference attendees.

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