The Week In Review: Design

Numbers

EDA and IP sales increased 5.6% in Q2 to $2.013 billion, up from $1.907 billion in the same period in 2015, according to the most recent Electronic System Design Alliance numbers. Asia/Pacific revenue increased 10.9% to $608.1 million; Japan increased 15.7% to $211.4 million. The Americas increased 4.4% to $908.4 million.

IP

Cadence launched the latest generation of its Xtensa processor architecture. The LX7 architecture increases floating-point choices from 2 to 64 FLOPS/cycle and includes click-box options for the Vision P6 DSP for image and convolutional neural network (CNN) processing, the Fusion G3 DSP for multi-purpose fixed- and floating-point applications, and enhancements for ConnX BBE DSPs for baseband and radar applications with optional vector floating-point units.

NetSpeed Systems unveiled the latest version of its cache coherent network-on-chip IP for heterogeneous multicore SoC designs for cloud computing, automotive, mobile and IoT applications. The interconnect uses machine learning to model the system as a whole and supports up to 64 fully cache-coherent CPU clusters, GPU blocks and other coherent compute blocks and up 200 I/O coherent and non-coherent agents.

Memory

Open-Silicon taped out the first High Bandwidth Memory (HBM2) IP subsystem in TSMC’s 16nm FF+ process in combination with TSMC’s CoWoS 2.5D silicon interposer technology. The full IP subsystem solution includes an HBM2 controller, PHY and interposer I/O, is available for 2.5D ASIC design starts and also as a licensable IP subsystem.

Deals

Arteris inked a deal with Mobileye, which licensed Arteris’ FlexNoC interconnect IP, as well as FlexNoC Physical and FlexNoC Resilience Packages for use in its next-generation EyeQ5 vision-based SoC family. Mobileye, a longtime customer, cited data protection technologies and automation features.

Siemens Building Technologies adopted Mentor Graphics’ SystemVision multi-discipline collaboration environment for its PCB design teams to explore concepts, validate performance specifications, and investigate architectures of systems developed for modern, energy-efficient building systems.

More TSMC Updates

Synopsys and TSMC collaborated on technologies for TSMC’s High Performance Compute (HPC) Platform on the 7nm process. Jointly developed technologies include via pillar, multi-source clock tree synthesis (CTS) with hybrid clock mesh and automated bus routing to match resistance and capacitance on critical nets.

Cadence’s digital, signoff and custom/analog tools were certified for the latest Design Rule Manual and SPICE for the TSMC 7nm process. Cadence also made enhancements to the 7nm Custom Design Reference Flow and library characterization flow.

M&A

Imagination’s digital radio business, Pure, will be sold to AVenture AT GmbH, an Austrian company, for £2.6 million in cash. AVenture has also been granted an option to acquire one of Imagination’s properties in Kings Langley, Hertfordshire for £4.5 million.

Standards

USB-IF announced the USB Audio Device Class 3.0 specification, aiming to establish audio over USB Type-C as the primary solution for all digital audio applications. According to USB-IF, the specification makes it easier to support digital audio over USB, add capabilities to reduce power consumption and add support for new features such as hotword detection.

Events

Thinking about DAC yet? The technical committee is seeking contributions on design research, design practices and design automation for the Research Track, Designer Track and IP Track. The first deadline is November 15, 2016.