The Week In Review: Design

Tools

Synopsys revealed a comprehensive low power reference kit for design and verification based on a bitcoin mining SoC design. The kit is designed to help accelerate deployment of a Unified Power Format (UPF)-based hierarchical design methodology and as a learning vehicle for the complete Synopsys low power flow.

Space Codesign introduced the latest version of its simulation environment to validate and predict performance of early-designed applications. The tool allows system designers to run the exact algorithm but on different targets without the need to duplicate functional elements.

Mentor Graphics, Luceda Photonics, and Imec teamed up on a full flow PDK for Imec’s integrated Silicon Photonics Platform (iSiPP50G). The PDK contains library symbols, PCells, simulation models, and a Tanner Calibre One IC physical verification rule deck.

Synopsys released the latest version of its software for the design of optical communication systems and photonic integrated circuits at the signal propagation level. The new version adds library elements for short-reach optical communications systems and PICs, as well as new modeling features.

IP

ARM unveiled a new technology for ARM Cortex-A CPUs, DynamIQ. It has a single cluster design with up to eight heterogeneous CPUs, allowing for different configurations of big and LITTLE processors, dedicated processor instructions for machine learning and AI, and a redesigned memory subsystem shared across all cores within the cluster.

Synopsys uncorked the DesignWare tRoot H5 Hardware Secure Module (HSM) with Root of Trust to protect sensitive information and data processing within an SoC. The HSM incorporates hardware cryptography acceleration, multi-stage secure boot, and secure instruction and data controllers to protect access and detect runtime tampering in external memories.

Deals

Samsung Electronics licensed Arteris’ FlexNoC interconnect IP for use by its foundry customers.

Renesas used the Cadence Perspec System Verifier to verify its new micro-controller unit design for IoT applications. Cited were improvements to the system-level verification process that reduced the number of hours spent on test scenario generation by up to 90%.

Legal

A federal appellate court has affirmed an Oregon jury’s finding that certain features of Synopsys’ ZeBu software product infringed a Mentor Graphics patent. The court affirmed the lower court’s award of over $36 million in lost profits damages, and further ruled that Mentor Graphics may pursue treble damages for willful infringement of the ‘376 patent. In addition, the court reinstated Mentor’s patent on clock timing for emulators, and revived Mentor’s claims that Synopsys infringes U.S. Patent Nos. 5,649,176 and 6,009,531 for Mentor’s emulation technology. Synopsys’ ZeBu emulation systems no longer include the features found to infringe.