Top 10 Power Management Verification Issues

Things you need to consider for effectively managing voltage in low-power designs.

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By Bhanu Kapoor

We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power is a primary design criterion for bulk of the semiconductor designs now. Power is a key reason behind the shift towards multi-core designs as increase in power consumption limits increases in clock speed at the rate we have seen in the past.

Voltage is the strongest handle for managing chip power consumption. Power management techniques that leverage voltage as a handle are being extensively used in power sensitive designs. These techniques include: Power Gating (PG), Power Gating with Retention (RPG), Multiple Supply Voltages (MSV), Dynamic Voltage Scaling (DVS), Adaptive Voltage Scaling (AVS), Multi-Threshold CMOS (MTCMOS), and Active Body Bias (ABB). The use of the power management techniques also imply new challenges in validation and testing of designs as new power states are created.

We take a look at some of the main power management verification issues based on what I have heard from various design groups using these techniques. Here are what I consider to be the “Top 10” power management verification issues, not in any order though:

  1. Reset out of wake up: Since different parts of design are awake in different modes of operation, managing reset out of power up is more complex and must be diligently managed.
  2. Power Connectivity: Now that you have several power supply signals connecting different parts of the design, you must ensure supply correctly reaches its designated destination only.
  3. Always-on Buffers: Some signals in a power managed designs must be always-on and ensuring always-on buffers associated with those signals is a must.
  4. Power Domain Isolation: The switching of power implies domains outputs must be isolated properly; also, inputs depending upon the design methodology.
  5. Power Switching Management: Ensuring correct enables to power switches and chaining of power switches to control amount of logic waking up in power sequence is necessary.
  6. Power Controller Design: Power state controller must ensure correct signaling for domain switching, isolation, retention etc. based on the power management architecture needs.
  7. Level-shifting: Signals that cross voltage domain boundaries need to appropriately level-shifted, and sometimes level-shifted and isolated, on all domain crossings.
  8. Power Sequencing Protocol: Power on/off, isolation, retention, clock gating, and voltage changes must follow a signaling protocol to ensure proper working of the design.
  9. State Retention: If retention is used with power gating, it is necessary to ensure correct retention upon wake-up whether using state retention power gating registers or save-and-restore via memory.
  10. Decap: As multiple power domains are created, ensuring that correct decap cells have been used and connected is necessary.

There are other power management verification issues and depending upon how you have been bitten in the past, they may make your top 10 list. It will be good to hear your experiences with these.

Bhanu Kapoor is the founder of Mimasic, a low-power consultancy.


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