TSMC’s Plan For Closing The Communication Gap

TSMC held its North American Open Innovation Platform (OIP) Ecosystem Forum at the Santa Clara County Convention Center on Sept. 25, providing a quick roadmap update and to recognize its partners for all the collaborative work needed to keep the TSMC innovation train rolling and enabling its customers to utilize the latest technologies.

L.C. Lu, TSMC fellow and vice president of R&D, said there is no change in the roadmap since last spring’s Tech Symposium. N3E is in production now, with N2 slated for next year, and A16 for the end of 2026.

Fig. 1: TSMC’s Advanced Technology Roadmap.

Lu also provided some motivation for TSMC’s Compact Universal Photonic Engines (COUPE).[1]

Figure 2 shows the “communication gap” that has arisen due to the tremendous increase in computing performance (~60,000X) while the bandwidths for memory have only increased ~100X, and an even lower 30X for I/O. The data for this plot is also available in AI and Memory Wall [2] by Amir Gholami.

Fig. 2: Communication gap challenge for system integration bandwidth.

Not only is there a large gap between the increase in compute and memory bandwidth, but the energy per bit that’s necessary increases by orders of magnitude as the communication moves from in-package to on-board to off-board, as shown in Figure 3 (below).

Fig. 3: BW Density * Energy Efficiency vs. Max Interconnect Distance, [G. Keeler, DARPA ERI 2019].

Ideally, we’d like to have the energy efficiency of using optical communication without having to pay the penalty of going off board. This is where COUPE comes into play.

Fig. 4: Silicon photonics markets.[3]

Figure 4 shows a slide from “COUPE Reference Flow Synopsys/Ansys,” presented by Remco Stoffer, photonic solutions product owner at Synopsys, and Lucy Yin, R&D engineer at Ansys. The key building blocks for a photonics IC are nicely shown in the diagram above, along with a list of other photonic devices and electrical components. An important part of this concept is being able to closely couple the photonics IC (PIC) to an electronics IC (EIC). Some of the markets where this technology will have an impact are listed on the right.

Fig. 5: Projected silicon photonics market size.[4]

Figures 5 & 6 are from “Design of Vertical Fiber-to-Chip Coupling System in TSMC’s COUPE Silicon Photonics platform for Co-Packaged Optics and In-Package Optical I/O Applications,” presented by Federico Duque Gomez, lead R&D engineer at Ansys. Figure 5 shows an ~9X projected growth in the market from 2022 to 2028 along with several use cases.

Figure 6 (below) shows a diagram of a co-packaged system along with challenges. This diagram shows a PIC mounted to a substrate and an EIC mounted on top of the PIC. This keeps all the components in the same package leading to that energy efficiency gain that we were looking for back in Figure 3.

Fig. 6: Co-packaged optics.[4]

Each step requires its own tools for addressing its unique design challenges. Since the OIP Ecosystem Forum is a venue for TSMC and its partners to showcase their advances, Figure 7 (below), which was presented by TSMC’s Lu, shows the vendor readiness for implementing COUPE designs. Looking at this chart it’s clear there are synergies between the Synopsys and Ansys tools that likely were important aspects in driving a closer relationship between the two companies.[5]

Fig. 7: COUPE tool readiness.

The chart shows that vendors have tools that are ready today to support design flows for COUPE, which should help enable that projected 9X growth from 2022 to 2028. COUPE is another important step forward in terms of making systems more efficient, while also leading to higher performance.

References

1. H. Hsia et al., “Heterogeneous Integration of a Compact Universal Photonic Engine for Silicon Photonics Applications in HPC,” 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 2021, pp. 263-268.
2. A. Gholami, “AI and the Memory Wall,” https://medium.com/riselab/ai-and-memory-wall-2cb4265cb0b8, March 29, 2021.
3. R. Stoffer, L. Yin, “COUPE Reference Flow Synopsys/Ansys,” TSMC 2024 NA OIP Ecosystem Forum, Sept. 25, 2024.
4. F.D. Gomez, “Design of Vertical Fiber-to-Chip Coupling System in TSMC’s COUPE Silicon Photonics platform for Co-Packaged Optics and In-Package Optical I/O Applications,” TSMC 2024 NA OIP Ecosystem Forum, Sept. 25, 2024.
5. “Synopsys to Acquire Ansys, Creating a Leader in Silicon to Systems Design Solutions,” https://news.synopsys.com/2024-01-16-Synopsys-to-Acquire-Ansys,-Creating-a-Leader-in-Silicon-to-Systems-Design-Solutions, January 16, 2024.