Understanding Power-Aware Verification

By Bhanu Kapoor

We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power consumption has become one of the most important differentiating factors for semiconductor products due to a major shift in the market towards handheld consumer devices. Power is a primary design criterion for the bulk of semiconductor designs now, and it’s a key reason behind the shift towards multi-core designs as the increase in power consumption limits increases in clock speed at the rate we have seen in the past.

Voltage is the strongest handle for managing chip power consumption. Dynamic power is proportional to the square of supply voltage and leakage power has a linear relationship with it. In addition, leakage power has an exponential relationship with the threshold voltage of the device. Power management techniques that leverage voltage as a handle are being extensively used in power sensitive designs. These techniques include: Power Gating (PG), Power Gating with Retention (RPG), Multiple Supply Voltages (MSV), Dynamic Voltage Scaling (DVS), Adaptive Voltage Scaling (AVS), Multi-Threshold CMOS (MTCMOS), and Active Body Bias (ABB). The use of the power management techniques also implies new challenges in validation and testing of designs as new power states are created.

There are some significant new challenges in validation of designs using above mentioned techniques as new power states are created in the design. At the physical level, dealing with multiple power supplies and variable power supplies present us with many new verification challenges. Can all of the power issues be addressed at the front-end in the context of simulation-based and formal validation techniques? Or is it unrealistic to even think that any true verification is possible without taking the back end into account? Or is this just one of those over-hyped problems? Some of the largest-volume consumer electronic products are using these techniques. How are the companies that design these chips getting them working in these products? How is power management of multi-core and many-core systems getting validated today?

Power-aware validation is a major concern for designs that are leveraging leading-edge power management techniques. If you are working through the challenges, I would love to hear your experiences.

Bhanu Kapoor is the founder of Mimasic, a low-power SoC design and verification consultancy.